ISSN 0970-3993 67 November 1988 ©lekfe Rs. 8.00 electronics THE PRACTICAL MAGAZINE WITH THE PROFESSIONAL APPROACH 11.05 THE MICRON PROBLEM MAGNIFIED Two public sector enterprises, Indian Telephone Industries (ITI) and Semiconductor Complex Ltd. (SCL) are aspiring to acquire the 1.5 micron technology. This sophisticated technology is indispensable for future telecommunication equipment. ITI Is keen on importing this technology from the VLSI of USA. SCL, on the ether hand, claims that it has already developed two micron technology and with further scaling up of facilities, it would be able to deliver 1 .5 micron chip to ITI. Smaller the size and greater the capacity of the chip is the concept behind this technology. The two organisations are unable to arrive at a common programme and if the ITI proposal Is approved, it may cost the nation in foreign exchange worth Rs. 60 crores. ITI. which is reluctant to join hands with SCL, will have to import semi-processed 1 .5 micron chips from VLSI and assemble it at Bangalore. In effect, the hl-tech process would be completed in the USA. For this assembly process and design, ITI has to pay 2.4 million dollars. In the alternative, for complete technology transfer ITI will have to pay 30 million dollars for capital equipment and another 30 million dollars for the manufacturing facilities. In other words, ITI will have to set up a new unit at a cost of Rs. 72 crores. SCL is prepared for a tri-partite agreement involving both the ITI and the VLSI of USA. It is common knowledge that the existing market for chips does not justify another unit while the existing SCL unit can deliver the goods with marginal investment. The decision here is not beset with any complex issues. Hard-headed, practical decision is called for. ITI and SCL would do well to join hands in mastering the art of miniaturisation. Front cover This month, we present a build-it-yourself range finder suitable for measuring dis- tances between 25 cm and 6 metres. It is based on the measurement of the time taken by a sound wave to cover a cer- tain distance. THE RISE AND RISE OF A MISSIONARY - SAM PITRODA O ome called him the messiah of In- dian telecom. Sam wanted himself to be known as Mr. Telecom. Sam Pitroda earned his place in Indian history of development and stays put for completing four other mis- sions, in addition to his own-tele- com mission. After accomplishing the first goal, the Centre for Development of Telematics, in 36 months; with an investment of Rs. 36 crores, the second three-year telecom mission has just completed its first year. This provides an occasion for us to look at die past few months and the future as well, with Sam Pitroda as the centre piece. The success story of Sam Pitroda in the United States may pale into insignificance before his ac- complishments in India in the last four years. Where hot and humid weather conditions prevail with fre- quent failure of air-conditioning equipment adding to the misery, where stuck up elevator and dead phones are a routine feature, where meeting the deadline of a project is a rare feat and cost overrun is al- ways a rule, Pitroda provided a striking contrast by making possi- ble “the impossible”. C-DOT met its target on the dot “C-DOT s development of die indi- genous switching systems that we have seen are even more important when we look at the manner in which it has been done ... within the stipulated time, without any cost overruns which is within the budgeted amounts, quite unlike odier government projects where we seldom see things happening on time and where we seldom even know or have any wild idea of what the cost will be by the time die scheme or project is anywhere near completion” This was the state- ment of the Prime Minister, Mr. Rajiv Gandhi, when C-DOT made its “Report to the Nation” on Oc- tober 1, 1987. If you ask Pitroda what are the achievements of C-DOT, he would not reel out die production of 188- line Rural Automatic Exchange, Private Box Exchange, tiiis pro- duct or that product. The real achievement is, says Pitroda, “that we have convinced ourselves that if we can create die right work envi- ronment, die right work culture and die right work standards in tune with the needs of our younger people, diey can create miracles. That is die achievement This hap- pens to be in telecom today. ” “Everybody said it could not be done. It has been done. May be in real life usage of die equipment, die project got delayed by a few' months. When people say, you are late by six months, it is not worth paying attention. We were in- terested in setting up the process. Product was important because without product, we could not have set up a process. Having initiated the cycle, the more important as- pect was the process of delivery and not necessarily the product of deli v- ery." “We have trained 400 people in C- DOT. We have new work etiiics and work standards. The larger question to ask now is whetiier we can do the same tiling in transport sector, energy, water and liealdi.” Pitroda compares the C-DOT as a “bvpass surgery in telecom” and it has given rise to die tiiought if simi- lar bypass surgery can be done in other areas. This is an accomplish- ment Of course, tiiere are always spin-offs. One can quote numbers, jobs created, lines manufactured, foreign exchange saved and so on. Even if decision-makers are willing to do bvpass surgery in other areas, the system is not yet ready for that says Pitroda. By system, Pitroda means these: With Rs. 5,000 in hand, if you want to open a bank ac- count, someone should identify you. For example, If I want to set up a factory and make a product without any government aid or foreign exchange, why should I need a licence? Take the case of a controller ofacommodity which is widely used and needed in indus- try. When someone suggested that the department of a controller was a misfit now, the question of 400 employees in that office came up. How could they be sacked. Pat came a solution that instead of cal- ling it controller’s department, let us make it a “promotion authority”. This is what is happening in our system. “You need a shrewd surgeon to per- form bypass. You don’t have people like that Bypass cannot be done by those who are interested in being liked by everybody; being worried about what others might say; want- ing to be friendly with the world. Some amount of administrative re- form has to come. That is coming as a part of the process but that is still slow”, according to Pitroda. Knowing Pitroda’s aversion to foreign technology and desire for self-reliance, it is logical to expect C-DOT to dominate manufacturers in the Indian scene. But, Pitroda disagrees with the idea of domi- nance. “I am more interested in the process. If a C-DOT licenced man- ufacturer does something original to the technology we have de- veloped, it is manufacturer’s technology. I will be proud to say that it is a great idea. ” “If 10 people left C-DOT tomorrow, I expect 50 more to leave. I am not worried. I say it is a healthy sign. I will like 100 people to leave. We have a different perception. ” The place for indigenously de- veloped technology in Indian tele- com is assured absolutely in the next couple of years. The trend is already set It is irreversible. That process is over. Those who de- nounce the trend may belong to vested interests, multinational cor- porations or those making spare parts or commission agents. On motivating people, this is what Sam says: What I try to do is basi- cally to articulate the objectives, give them clarity of pur- pose, give them a long-term vision, see how they get fixed-in and break up their task into manageable, tan- gible, deliverable milestones. I give them hope and kill cynicism. I kill cynicism and sometimes overdo it ” Sam Pitroda does not meddle with the day to day problems of C-DOT anymore. He does not even know what his people are doing. For example, the 1988 plan was pre- pared by his colleagues. He made a few comments here and there. On October 1, they began the planning process for 1989. Lot of discus- sions and debate, gyrations and commotion take place before die document is prepared. The C-DOT plan document is distincdy diffe- rent from the rest It has only two things-activity with date and die name of die persons who will do die job. Later, in July next, the August 1984: C-DOT starts work on digital switching in India. July 1985: First call placed through PBX in laboratory. August 1985: Inauguration of 128- port PBX takes place. September 1985: PBX demon- strated to Prime Minister. March 1986: Rural exchange (RAX) installed at Kittur field trial site. May 1986: RAX cutover takes place at Kittur. September 1986: C-DOT partici- pants in Africa Telecom 87 at Kenya. December 1986: Manufacturers' as- sociations formed. January 1987: Agreement signed with ITI to transfer RAX technol- The claim ofindigenisation, invari- ably elicits a query on the indigen- ous content in a product or project Pitroda, riglidy, spurns such mun- dane definition of indigenisation. “what is die definition of indigeni- sation? Is it only applicable to parts? Let us say, die bill of a pro- duct is 100 dollars. It has 50 dol- lars wordi of material brought from abroad. Does it mean, 50 per cent indigenisation? This 100 dollar could give rise to 700 dollar wordi of products. Installation, cabling, maintenance engineering and so on also constitute a part of the pro- ject The percentage would not mean anything. ” Today, in C-DOT system, roughly 40 per cent of the components are imported and most of them are ICs. In six months. Semiconductor Complex Ltd. will produce them. Then, the import content will be less than 10 per cent which will be microprocessors and memory. The C-DOT system is to be man- ufactured by nearly two dozen com- panies. There is a competition now. In, the past ... it was a seller’s market As soon as a system was produced, there was someone to lift and the price was dictated by the manufacturers. C-DOT has changed the situation. The price for a line was around Rs. 5,000 before and it has now come down to Rs. 2,400. The media has made much about Pitroda’s aversion to the introduc- February 1987: C-DOT participates in Indiacom 87 in New Delhi. March 1987: 10,000 calls simulated on main exchange (MAX); Second C-DOT telecom mission approved. May 1987: RAX installed at Churhat. June 1 987: MAX installed at field trial site in Delhi. July 1987: RAX phase II DOT evalu- ation commences. August 1987: 5000-port MAX dem- onstrated at Ulsoor; inauguration of ITI/C-DOT factory takes place; C-DOT completes first technology mission; participation by C-DOT directors and Sam Pitroda in the South Asian Association for Re- gional Cooperation (SAARC). September 1987: Second technol- ogy mission commences. tion of the cellular telephone in India. What exactly are his views? Explains Pitroda: “Let us not con- fuse cellular phone with earphone. Car phone is something we do not need in this country at this stage. In a country with 250 district head- quarters which are not connected to STD, how can you afford to give 5000 people the car phone? The system around me is not efficient Then, how can I be efficient? The train may not arrive in time. The driver may not come on time. My meeting will begin 20 minutes late- So, die system has to be in tune with the field. We are not ready yet to have the car telephone. Widi car telephone now, the only thing I can do is to tell my wife I will be late for dinner. Money can be better spent elsewhere.” plan progress will be reviewed. Some major C-DOT accomplishments ogy- CENTRONICS INTERFACE FOR SLIDE FADER The slide fader published earlier this year was originally designed for use with MSX computers. To further boost the interest in this versatile and simple-to-build circuit, an interface was developed that allows the fader to be driven from a standard Centronics port, which is available on practically any type of home computer. The slide fader discussed in Ref. <■> is a computer peripheral that makes it poss- ible to control up to four slide projectors independently. Slide carriage control (forward/reverse) and lamp intensity (in 64 steps) are programmable on the com- puter. To keep the operation of the cir- cuit as simple as possible, one 8-bit out- put port is, in principle, required for each projector. The interface circuit de- scribed here effectively extends the num- ber of ports from one to four. One Cen- tronics port can drive up to four inter- faces of the type described here, so that the computer can program up to 16 in- dividual slide projectors. The Centronics port: universal and flexible The Centronics parallel printer port is an input/output connection composed of 8 data lines, two ground connections, 3 handshake lines and a number of other lines for printer control. Virtually any modern (home-) computer is equipped with a Centronics outlet, whose pinning and handshake protocols have gained worldwide acceptance. On IBM PCs and compatibles, the Centronics port is usually identified as LPT1:. The timing diagrams of Fig. 1 show two handshaking arrangements on the Cen- tronics port. In the so-called STROBE/ACK (‘normal’) protoco l, the peripheral device activates ACK (acknowledge) after recep tion of the ris- ing edge of the STROBE signal supplied by the computer. This is not allowed to send new data to any peripheral connec- ted to the port, before it has received the ACK pulse. When the peripheral has processed the data, it indicate s read iness to accept new data by making ACK logic low. Some computers work with the STROBE/ACK protocol, some with the slightly more complex STROBE/ACK/BUSY protocol, while 1 1 .24 elektor India november 1988 Now all computers sporting a Centronics outlet can be connected to the powerful slide fader published earlier this year. PARALLEL DATA W7777777777777\ BUSY/ACK PARALLEL OAT A W/i/WlIim B '.0 1—1 •-> ACKNOWLEDGE «» 1- Fig. 1. Basic liming of the two handshaking arrangements commonly used on the Centronics still others can handle both. The inter- face circuit described here has been de- signed to support both handshaking protocols. Pori expansion: from one to four Briefly recapitulating the operation of the slide fader, the 8-bit dataword it receives from the computer is composed of three functional blocks: • databits DO to D5 to determine the lamp intensity in 64 (2 fi ) steps; • databit 6 to control the loading of the slides, and the reverse movement of the carriage; • databit 7 for the same function, but in forward direction. D6 and D7 are never logic one at the same time. This combination, however, makes it possible to design a circuit that distinguishes between a projector dataword and a projector selection word. With D6 and D7 both logic high in the 8-bit dataword sent to the slide fader, 6 bits remain to select up to 16 projectors. Figure 2 shows that databits D2 through D5 in the projector selection word are used for selecting projector 1, 2, 3 or 4. Note that these are off when the associ- ated bit is logic high. When more than one projector is selected at a time, all of these receive the same dataword. The two remaining bits, DO and Dl, are used for selecting one of four projector blocks. Circuit description With reference to the circuit diagram in Fig. 3, ICj, ICs, 1C(. and IO form the 8- bit output ports that control one slide projector each. The interface is connec- ted to the Centronics outlet of the com- puter via connector Ki. R-C low-pass networks at the inputs of data buffer lC.i suppress interference on the datalines. ICj is permanently scjectcd because its enable inputs, G2 and Gl, are hard-wire d to grou nd. Bistable FFi is set by the STROBE pulse, so that BUSY is activated via output Q. Output Q goes low and discharges Ci via R2. Afte r a prede fined period, the level at in- put CLEAR is sufficiently low for the bistable to be reset. Output Q toggles and de-activates BUSY, while Ci is charged again by Uie logic high level pro; vided by output Q. The rising edge of Q triggers a second bistable, FF?, whose operation is similar to that of FFi. The short, negative-goi ng, p ulse at the Q output forms the ACK signal for the computer. The fixed handshake timing used here is fairly crude, but this is of little consequence in practice, since the speed of the circuit allows it to latch data on the negative edge of the STROBE signal. This is in contrast to a printer, which often needs considerably more time to transfer the information on to paper. Connector K2 allows up to four inter- face circuits to be chained, so that up to 16 projectors can be controlled. Compo- nents IC2, R2, R3, Ci and C2 are only re- quired on the first interface in the chain, i.e., the one connected to the computer’s Centronics port. K2_carries 8 buffered databits, XO and XI, ground, and the STROBE pulse. The PAL (programmable array logic) in position ICi combines the functions of a number of digital integrated circuits, and thus keeps the chip-count of the cir- cuit relatively low. This, in turn, economizes on board space. Figure 4 shows the internal configuration, after programming, of PAL Type 16R4 (this is available ready-programmed through the Readers Services). The chip combines databits DO through D7 with the STROBE pulse to generate the clock signals for latches ICj, ICs, IC6 and IC?, and also separates projector datawords from projector selection words. This is done by gates N? through N10 in the PAL. Databits D6 and D7 are applied to pins X6 and X7. As already discussed, the difference between a dataword and a selection word is that in the latter D6 and D 7 are both logic high. If this is so when STROBE goes low, the output of N10 will remain logic high. It does not go low until D6 and D7 are simul- taneously logic low, or of complemen- tary logic level. The output of N10 controls three-state buffers internal to the 16R4. During the transmission of a projector selection word, buffer N2 is enabled, so that the proj.4 proj.3 proj. 2 00 =block 1 01 = block 2 11 = block 3 10 = block 4 output of Nu is logic low. Output buf- fers N 12 through Nis then block the out- put signals of the four bistables, so that the clock inputs of the registers in the in- terface circuit are held logic low by pull- down resistors Rj through R-. The four bistables, however, load the data applied to the D input. Since both the output of Nn and inputs X1-X2 of the selected in- terface board are logic low, the values of variables X2, X3, X4 and X5 determine the projector selection. XO and XI are the two bits that select one of four interfaces. For the first module, the combination is D0=0 and D1 =0. To select a projector, the D-input of the relevant bistable in the PAL should go logic low, so that the Q output follows this level after a clock pulse. When the dataword is sent, the output of Ni6 goes logic high, and the output state of each of the 4 bistables is transferred to the clock input of the associated register on the interface board. A logic high level at an output Q causes a positive-going clock pulse (CLK) that enables the relevant register to latch data from the databus. Any dataword that follows immediately, e.g., a carriage return (CR) code sent by the computer, simply does not reach the slide fader. The projector selection is erased during the writing of a dataword. Three-state buffer N 2 is switched to high impedance via N 10 , and its output is logic high due to pull-up resistor Ri. Data is read via the D inputs, and the Q outputs of the cards 1, 2, 3 and 4 are 00, 01, 11 and 10 respectively. Finally, constructors in possession of a PAL programmer will find the data for loading the 16R4 in Fig. 6. aid of short M2 bolts and nuts. Kj is a similar header with 50 pins. It may be omitted when the Centronics interface card is Fitted on to the slide fader card — in that case, connect the two cards with a short length of 50-way flatcable bistables follow the data level. This means that it is impossible for a second positive edge to appear on the CLK out- put of the Centronics interface when a second dataword is being sent. Any pro- jector dataword should, therefore, be preceded by a projector selection word. It is not possible to send two successive datawords. To select a Centronics interface card, both X0 and XI should be logic low. Selective addressing of one-of-four in- terfaces is achieved by swapping and in- verting X0 and XI on each module as shown in Fig. 5. The selection codes for Construction Figure 7 shows the compact printed cir- cuit board designed for the Centronics- to-slide fader interface. Start the con- struction with fitting the wire links. Connect the two points marked A with an insulated wire, and do the same with the two points marked B. The jumper block below ICi is best made from a 6- way straight PCB header and two jumpers. On module 1, install the two jumpers in positions X, on the other modules in positions Y. Ki and K 2 are 14-way, male, angled, headers with eject handles, secured on to the PCB with the Fig. 6. Programming information for PAI. Fig. S. Up to four Centronics interface cards can he addressed individually by connecting 16K4. This chip is available ready them in series, and swapping and inverting the X0-X1 selection lines. programmed through the Readers Services 11.27 Fig. 7. Compact single-sided printed circuit board for the interface card. soldered direct to the PCB connections. The Centronics interface is conveniently powered from a mains adaptor capable of supplying 8 to 10 VDC at about 250 mA. Software: the finishing touch Programming the slide fader via the Centronics interface described here re- quires sending two successive characters — first the projector selection word, then the projector dataword. The LPRINT command available in BASIC is eminently suited to controlling the slide interface, because it provides a direct route to the Centronics port. As an example of how software can be developed, assume that the lamp in pro- jector 2 is to light at full intensity. No other functions are required. First, send 1111 OIOO2 (244d; F4n) as the projector selection word, then 0011 1111 (63d; 3Fh) as the projector dataword. In BASIC, this corresponds to LPRINT CHR$(244);CHRS(63). This instruction causes the lamp in pro- jector 2 to light at full intensity. To obtain the correct character-string codes for a given projector number, P, and block number, B, use the equation: LPRINT CHR$(252- 4*2'' + B);CHR$(data) A more universally applicable instruc- tion in GWBASIC is shown in line 210 of the demo program listed in Fig. 8. Some versions of BASIC have a built-in output filter that translates CHR$(9), the tabulation (TAB) character, into a series of spaces (ASCII code 32d). This filter should be turned off with an appropriate instruction. A semicolon (;) should be used to delimit printable characters. Depending on the speed of the PC runn- ing the demo program of Fig. 8, and the type of slide projector used, it may be necc ry to assign different start values to variables S (dissolve speed), F, R and T (carriage movement). Use different values for F and R to enable using pro- jectors with single-key control. All pro- jectors used are identified in hexadeci- mal notation in string AS (line 40). slide fader board. interface secured Prototype of the Centr PERIPHERAL MODULES FOR BASIC COMPUTER from an idea by J. Haudry The 8052-based single-board process and control computer introduced in <» is a system designed with hardware expansion in mind. This article describes two modular input/output boards that are indispensable when the BASIC computer is to control digital or analogue peripherals. Just for those who do not know: the sys- tem described in reference ll) is a single- board computer based on Intel’s Type 8052AH-BASIC vl.l microcontroller. As indicated by the type number, the computer can be programmed in BASIC. Programming is done with the aid of a dumb terminal (or a host com- puter running a terminal emulation program), and a bidirectional RS232 link to the BASIC computer. The system can run programs from an on-board EPROM, and is, therefore, ideal for small-scale process and control appli- cations (‘turnkey’ systems). Interesting- ly, control software is written and debugged direct on the system, and loaded into EPROM by the CPU, i.e„ without the need of an EPROM pro- grammer. The BASIC computer has been one of the most popular projects published over the last year or so in this magazine. Users have found it simple to build, program, and connect to existing equip- ment. The BASIC interpreter in the 8052AH-BASIC is relatively fast, and supports a number of extremely useful bit-manipulation commands. Machine code programming is also possible when the Intel reference guide is available. After our publishing of the ‘bare bones’ of the BASIC computer, many users have expressed a firm interest in in- put/output extensions for connection to the available bus. The modules described here are our answer to these requests. Readers may be interested to know that the modules are also compatible with a 8751-based autonomous input/output controller with RS232 interface, to be described in a forthcoming issue of this magazine. 11.30 Fig. 1. The inpul/outpul system for the BASIC computer is a modular structure that gives the user freedom of configuration. The I/O boards are connected direct to the databus of the microcontroller, hut are addressed in the memory segment reserved for peripheral circuits. Functional description of the I/O modules Two types of bus-connected module are described here: • a bidirectional digital interface with 8 inputs and 8 buffered outputs; • an analogue output module capable of supplying a highly accurate output voltage between 0 and + 10.23 V, in steps of 10 mV. Between the BASIC computer’s bus and these modules sits a simple address decoder. The I/O modules are small units, and one address decoder allows parallel connection of up to 8 digital modules, or up to 7 modules when analogue and digital types are used sim- ultaneously. The BASIC computer itself allows the connection of a maximum of two address decoders. The modular structure of the expanded BASIC com- puter is illustrated in the block diagram of Fig. 1. The address decoder provides a bus in the form of a flatcable, which runs from one I/O module to the next. Address decoder for I/O modules The circuit diagram of Fig. 2 shows the simplicity of the address decoder for the Fig. 2. The interface shared by the I/O modules is composed of an address decoder that divides the available memory space for I/O in 8 blocks of 256 addresses, and a cir- cuit that modifies the timing of the WR pulse to ensure correct loading of the D-A con- I/O modules. Monostable IC 2 is used for timing one of the control signals for the 10-bit digital-to-analogue (D-A) con- verter. The presence of address lines All and A12 allows defining two address ranges, so that two decoders can be mounted in parallel, each with a different jumper configuration (A-D). Table 1 shows that each card occupies 256 addresses. Address decoder ICi supplies 8 enable signals, EO to E7. The special use of E7 on the analogue output module will be reverted to, as well as the function of signal BS, which is supplied direct by the BASIC computer, and runs to the analogue output board(s) via the address decoder board. Monostable IC 2 changes the timi ng of WR to provide a signal called SWR Fig. 3. Circuit diagram of the bidreclional digital interface. Up to 8 of these circuits can be controlled by a single address decoder. (short write or special write), needed for controlling the D-A converter on the analogue output module. Bidirectional digital input/ output module The circuit diagram of this basically simple unit is given in Fig. 3. Circuit ICi is an octal latch whose inputs are connected to the databus of the BASIC computer. Data is latched into ICi on the risi ng edge of the memory write signal, WR, but only when input G is held logic low. This condition is satisfied when the address supplied by the com- puter falls within the range preset by the jumper on block Kj (see Table 1.). When the processor writes a databyte to a digital output, e.g., at address F6OO11, jumper E6 should be installed on K>, and jumpers BD and AC on the address decoder board (Fig. 2). Circuit IC2 is controlled by the same en- able line, Ex, as ICi, and in addition by the read signal, RD, of the microcon- troller. As a further configuration example, jumper E4 should be installed on K.i, and jumpers BC and AD on the decoder board, to enable the microcon- troller to read a databyte at address ECOO on the digital I/O board. The databyte read by the selected card is formed by the logic configuration of the Fig. 4. Internal diagram of the ULN2803 from Sprague. Each of the 8 surge-protected darlington transistors in this chip can switch (inductive) loads of up to 500 mA. signals applied to inputs 10 to 17 on the The Type ULN2803 in position ICj is 25-way D connector, K2. Note that the an 8-way inverting power buffer corn- input lines have pull-up resistors, so that posed of high-voltage, high-current dar- any non-connected input is read as a lington transistor arrays. This IC enables logic high level The pull-up resistors the digital output to directly control a allow the digital input to be connected wide range of loads, such as relays, direct to an existing open-collector or solenoids, stepper motors and LED dis- open-dram output. plays. Figures 4a and 4b show the inter- Fig. 5. The analogue output module is based around a 10-bit digital-to-analogue converter Type DAC1006 from National Semiconductor. The output voltage span is from 0 to 10.23 V in 10 mV steps. nal structure of the ULN2803. Note that the buffers are of the inverting type, and that internal anti-surge diodes are pro- vided to prevent damage to the open- collector output transistor when the cur- rent through the inductive load (relay coil) is interrupted. The anti-surge diodes are internally connected to a common rail, which is brought out to pin 10. This means that the supply voltage for the inductive loads controlled by the ULN2803 can be connected to pins 21 and 8 of K2. Analogue output module The heart of the D-A module shown in Fig. 5 is formed by ICi, a Type DAC1006. This 10-bit DAC is remarkable for its excellent stability and capability to be controlled from an 8-bit bus. Loading of data (0 to 1023 10) is done in two successive operations, under Fig. 6. For the DAC 1 006 lo operate corectly, data should remain stable on the the databus for at lea st 200 ns following the rising edge of the WR pulse (Fig. 6b), which is not so on the databus of the 80S2AH-BASIC (Fig. 6a; Fcl= 11.0592 MHz). A monostable multi- vibrator is, therefore, required to shorten the WR pulse (Fig. 6c). control of the logic level of the BS (byte ment as regards the duration of the select) signal applied to pin 3. This databyte. The timing diagrams of Fig. 6 signal comes direct from the microcon- show that databytes are present on the trailer 8052AH-BAS1C via an output bus for only 40 ps after the WR pulse line of port PI. Users should decide for (Fig. 6a). The DAC1006, however, re- themselves which of these lines is to be quires data to be present for at least used for providing signal BS. 200 ns (Fig. 6b). This problem is solved The Type DAC1006 has a few by monostable IC2 in the address pecularities which call for a rather decoder circuit (Fig. 2). Note that the special circuit configuration around it. 74LS122 used for this purpose is not Firstly, the DAC has a specific require- available in the HCT version. Fig. 7. The DAC 1006 exp ects 10-bit, right-justified, data in a 16-bit dalaword. Signal BS, together with WR and CS, is needed to ensure that data from the 8-bit databus is sequentially latched into the device. A further signal, XF'ER, effects the transfer of the complete dalaword from the latches to the internal conversion register. Fig. 8. Timing diagram relevant to the loading of data in the D-A converter. Loading the DAC The second peculiarity of the Type DAC1006 has to do with the way it is loaded with digital data. Figure 7 shows how signal BS allows the chip to latch the 10-bit dataword as 8, followed by 2, bits. Unconventionally, the 10 databits are left-justified in 16 available bit lo- cations. Fortunately, in spite of the slightly unusual configuration of lines ADO to AD7, and BO to B9, it is still possible to achieve right-justified data by multiplication of the right-justified original 10-bit data by 64. The first 8 bits are loaded when BS is logic high, the 2 remaining bits when BS is logic low (see also Fig. 8). Once the 10-bit dataword is available in the latches, it is ready to be transferred to the conversion register. This operation is controlled by signal XFER, which is simply Ex supplied by the address decoder board. This explains why only 7 boards can be connected to the address decoder when one or more analogue output cards are being used. In that case, line E7 is not available for enabling a digital I/O module because it serves to clock the transfer of the databits to the conversion register in the DAC1006. Figure 8 shows the time relation between the signals involved. As an example, the analogue output module is addressed by E0, while BS is provided by port line P1.0 of the 8052AH-BASIC. Smart users may still be able to use E7 for addressing an eighth card, even if one or more analogue output cards are being used. This is possible provided it is ensured that the contents of the latches are correct the moment the 8th card is addressed, and that the databyte written in the latch of the selected card by E7 (= XFER) is correct also (refer to the listing in Table 2). The external reference voltage for the DAC1006 is provided by Di, whose ther- mal coefficient can be accurately com- pensated by preset P2. From current to voltage The output of ICi supplies a current which is converted to voltage in opamp IC2. Preset Pi allows defining the full- scale value of the output voltage. The use of a relatively expensive opamp Type OP-77, which achieves an offset voltage of only 50 fts at an ambient temperature of 25° C, may be questioned given the step size of ‘only’ 10 mV. It could be argued that a more common- ly available opamp with an external off- set compensation resistor would give the same results as the OP-77. This is not so, however, because the external compensa- tion resistor would have a fixed value, while the output resistance of the con- verter chip changes with every new digital value loaded, due to the different configuration of the internal R-2R lad- der network. With reference to the simplified diagram of Fig. 9, the effect of this change on the static accuracy of the I-V converter can be expressed as the magnitude of the er- ror voltage, calculated from error voltage = V M (1 + Rf/Ro) where Ro is a function of the digital value written to the DAC: Ro^lO kS for more than 4 logic high bits; Re® 5 30 kQ for any single logic high bit. Therefore, the offset gain varies as follows: code = 001111111111: Vcni = Vm(l + 10 4 /10 4 )=2Vo>. code = 010000000000: Verr2 = Vo»(l + 10V3 X 10 4 ) = VjVos. The error difference between these values is ?4Vos. It will be evident from the above that the non-linearity of the output voltage is a function of the opamp’s offset voltage. When this is low (OP-77), the maximum deviation is also low, athough still de- pendent of the digital value written to the DAC. Construction and alignment The peripheral extension modules for the BASIC computer are three printed circuit boards (Figs. 10, 11 and 12) inter- connected by a bus formed by flat rib- bon cable. The layout of the boards is such that the output connector, K2, can be fitted onto the equipment front panel, with the board mounted perpen- dicular to this at the inside. At the other end of the cards, a 26-way flatcable plugged into Ki runs from one card to another, connecting all of these to the bus card, which is mounted on the BASIC computer. The total length of the cable should not exceed about 30 cm to prevent digital interference on the databus. The address decoder/interface card can be fitted direct on to the BASIC com- puter board, and is connected to it by a short length of flat ribbon cable. On the computer board, connect pin 7 of IC3 (address decoding signal Y7) to pin 8 of the 40-way connector (K2). It is also necessary to choose the Port 1 line to 880159 - 21 Fig. 9. Variation in output resistance of the DAC as a function of the converted code gives rise to a variable offset current at the in- put of the opamp, which translates current to voltage, and so magnifies the offset voltage. Obviously, the offset voltage of the opamp itself should be as low as possible. Fig. 10. Printed circuit board for the address decoder. supply BS. The connection between pin 6 of K2 and pin 19 of Ki shows that we have opted for Port 1 line PI. Any other line is equally suitable, as long as the software for the I/O modules takes this into account. If it is decided not to use the analogue output module, the last mentioned link can be omitted. Similarly, the ±15 V supply is not required then. The modules are ready after being assigned a memory address by placing a jumper on Ki. There are only two, simple, adjustments to carry out on the analogue output board(s). First, correct the temperature coefficient of the LM336-2V5 by ad- justing P2 for a reference voltage of 2.490 V measured at pin 6 of the output connector, K2. Next, write IOOO10 to the DAC (10 mV/LSB) and set the full-scale output voltage to 10.00 V with the aid of The I/O modules discussed have a rela- tively low current consumption, and are, therefore, conveniently powered from the existing supply for the BASIC com- puter. The analogue board draws about 10 mA, the digital board and the decoder each about 20 mA. Final notes The contents of the conversion register in the DAC1006 are not defined at power-on, so that the output voltage may not be nought then. When an XFER pulse is received by a DAC, all other DACs connected respond to this simultaneously. This means that the con- tents of the latches should correspond to the desired output voltage, which may not be the case at power-on. The analogue and digital ground lines may only be connected on the address decoder board. Table 2. Examples of elementary command routines For analogue module: 100 EO - 0F000H 110 XF - 0F700H 120 INPUT X 130 X - X • 64 140 PORTl - I 150 XBV(EO) - X/256 160 PORTl - 0 170 XBY(EO) * X.AN0.0FFH 180 XBY(XF) - 0 190 GOTO 120 For digital module: 10 El =■ OFIOOH REM module address (see K3) 20 Y - XBY(El) REM read input byte from Y 30 XBY(El) - 00F3H REM write byte F3 Fig. 11. Printed circuit board for the digital I/O module. Fig. 12. Printed circuit board for the analogue output module. When the logic outputs are used only for driving other digital circuits, the ULN2803 need not be fitted, and wire links may be installed between the PCB connections intended for the inputs and outputs of the chip. Finally, do not forget that E7 can not normally be used as a board- selection signal because it is needed as XFER shared by the analogue output modules. 1 1 .36 etektor india november 1988 Parts list OIGITAL I/O BOARD Resistors: Ri . . Ra incl.«100K Ra. . .Ri» incl.B 10K Capacitors: Cl = 10p: 16 V C2;C3 = 100n Semiconductors: ICt = 74HCT377 IC2 = 74HCT541 IC3 = ULN2803A Miscellaneous: Ki - double-row 26-way right-angled header, or 26-way right-angled male header with eject handles. K2= 25-way 0 connector, male, with right- angled pins. , K3= double-row 1 6-way straight PCB header. 1 jumper for mounting on K3. PCB Type 880163 PREAMPLIFIER FOR PURISTS The ideal preamplifier is a short piece of wire. Unfortunately, we have not reached that state yet. A practical preamplifier must match signal levels and impedances of the various units in the system. None the less, the preamplifier presented here approaches the ideal state: the electronics in the signal path have been kept to a minimum. Fig. 1. Block schematic of the preamplifier. Since the advent of the compact disc player, more and more music lovers have added one to their hi-fi system. In fact, the stage has now been reached where a great many hi-fi enthusiasts no longer, or hardly ever, use their conventional record player. The present preamplifier is aimed at these listeners. Their hi-fi sys- tem will normally consist of a CD player, a digital audio tape (DAT) player, a reel- to-reel tape recorder, a tuner, and a power amplifier. The block diagram in Fig. 1 shows the layout of the preamplifier. The control board contains 10 switches, each of which controls a high-quality relay. The relays select the various inputs and out- puts. In addition, independent input selection is possible for the two tape out- puts and the line output. This makes it possible to record from one signal source and at the same time to listen to another one via the loudspeakers. The two bus boards are adaptations of that used for the ‘Top-of-the-Range Pre- amplifier’ tn . It is one of the tasks of a preamplifier to match the input and output impedances of the various units in the audio system. Another one is volume control. These re- quirements are met by the buffer- amplifier, the only active element in the signal path. Bus boards Input and output sockets, relays and as- sociated components are housed on the same board as used in Ref. 1 — see Fig. 3. The shaded areas indicate the changes made for the present design: the components in these areas are not used. Bus board 1 contains the input and out- put sockets, the potential dividers that equalize the input signal levels, and the input selectors for the tape outputs. These selectors, controlled from the con- trol board, operate four high-quality relays, ReA to ReD inch. The relays determine which input signal is passed to the two tape output sockets. The board also houses the independently switched output sockets. Line output 1 is controlled by relay ReF on bus board 2, and line output 2 by relay Ref on bus board 1. This arrangement does not con- 11.37 I'iR. 2. Prototype of the preamplifier. Iradict the design criterion of using the shortest possible path, because the two boards are sandwiched in the construc- tion phase. Buffer-amplifier Apart from possessing the highest poss- ible audio qualities, the amplifier must (a) present a minimal load to the input circuit; (b) be equipped with a volume and balance control; and (c) have a low output impedance. Its circuit diagram is shown in Fig. 4. The difference between it and most other amplifiers of this nature lies in the choice of components. More particularly, the type of opamp is important. The one used here can not easily be bettered. Further, the use of 1% resistors is not intended to achieve high accuracy, but rather to ensure long-term stability. Only one capacitor is used in the signal path, and it is, of course, of the highest quality for audio purposes. No capacitors are used in the output of the amplifier, since the inputs of the power amplifier are normally fitted with one. In any case, the off-set voltage of the second stage is so low that even where a DC-coupled power amplifier is used no direct-voltage problems will ensue. The purpose of resistors Rj:, Rh, R jo and Rh is mainly to decouple the two outputs from one another. They are also of benefit where long connections or capacitive loads occur. In most cases they may be omitted (replaced by wire links). This is particularly so if only one output is used. The balance control is arranged as two independent potentiometers, one for each channel. This arrangement has the advantage that not only the balance but also the output level may be set in ac- cordance with the input sensitivity of the power amplifier. Control board The relays are controlled electronically. This has the disadvantage that after switch-off the amplifier no longer ‘remembers’ which input source was Fig. 3. The two bus boards are adaptations of that used in the very succesful ‘Top-of-lhe- Range' preamplifier." 1 Fig. 4 . Circuit diagram of the buffer-amplifier. selected, but the advantage that you don’t get blown out of your seat when on subsequent switch-on the tuner is tuned to a hard-rock programme and the volume is set fairly high. The control-circuit is so arranged that after switch-on no input source is selec- ted and that the user may select no, one, or two outputs. The control circuit may be divided into three parts: (a) one for the control of the output relays; (b) one for the control of the recording source relays; and (c) one for the control of the input source relays. The circuit of (a) is given in Fig. 7a. It is based on bistables FFi and FF2, which store the selected setting. Since the Q output of FF2 is connected to the D output, each clock pulse (generated when either Si or S2 is pressed) will toggle the relevant bistable. In this way, a selected output is switched off and a switched-off one is selected. To ensure smooth operation of the cir- cuit, the switches are connected to the clock input of the bistables via debounce circuits N1-N2 and N3-N4. The two circuits are intercoupled with the aid of diodes Di to D4 inch and resistors Rio and Ru in a manner that makes the interdependence between the relays comparable to that of mechan- ically coupled switches. This makes it impossible for two relays to be actuated simultaneously. Note that the diode-resistance logic is formed only by the relevant resistor, Rio or Ru, and the diode that is connected to the bistable, D2 or D4 as the case may be. The other diode, Di or Dj, only serves to prevent the output of the bistable being shorted to ground by the associated switch. Diode D2 and Rio, and D4 and R11, form and NAND gate. The output of that gate, i.e., the junction of the diode and resistor, is 0 only if the associated circuit output is selected and the switch of the other channel is operated. This ensures that when an output is selected, the other output is switched off. In spite of this arrangement, it is possible to switch on both outputs simultaneously. To achieve this, the sequence in which the switches need to be operated is import- ant. It is necessary for the switch associ- ated with the switched-off output to be depressed first and to be held down while the other switch is pressed. If this sequence is reversed, the outputs are changed over. If both outputs are switched off, it is permissible for both switches to be pressed simultaneously. To ensure that the bistables are in a given state on switch-on, their set and reset in- puts are provided with RC networks. If either C11 or Co is replaced by a wire link, the associated output remains off. If the capacitors are fitted as shown, the bistable output will be ‘on’ about a sec- ond after switch-on. Because of the relative large time- Fig. 5 . Circuit diagram of the power supply. Mg. 6. Component layout of bus board l.'" The second and third sections of the control board consist of identical circuits — see Fig. 7b. Circuit ICi is an eight-fold inverter- driver that prompts the actual control circuits around IC.i and ICj to provide the input relays and indicator LEDs with adequate current. The drivers are controlled by two BCD- to-decimal decoders, ICi and ICi, which are arranged in a manner to make it im- possible for either IC to switch on more than one input at a time. If more than one switch is pressed at the same time, (II Shaded Components not used no input is selected at all. This is achieved by the use of BCD codes of which only one bit is high: those for 1, 2, 4, and 8. These codes are generated when only one switch is pressed. The hold function is obtained by feedback of the relevant output via a diode. As soon as an output is high, it causes a code at the input which ensures that the output remains high. This state can be altered only by operating another switch: the decoder then changes over. During the change-over (which lasts for a few hundred nanoseconds), or if more than one switched is pressed (which may last longer), none of the input relays can be energized. If more than one switch is pressed at the same time, the decoder will be presented with several high bits. One of the six not-connected decoder outputs will then go high and all connec- ted outputs will become low. Resistors: Rt...R9 incl. = 1 MO Rto;Rn;Ri6. . .R23 incl. = 10K Ri2:Ri4;R24,R25 = 680R Ri3;Rib=4K7 R26;R34 = 1M0; 1% R27;R28;R36,'R36 = 22K 1 ; 1% R29;R37=47K5; 1% R30;R38 = 2K49; 1% R3t;R39= 10K; 1% R32;R33:R4o;R4i=47R Pi.;Pib-10K logarithmic potentiometer (Bourns, Spectroll Ptc=10K stereo logarithmic potentiometer (Alps) C7 = 470m; 40 V Cs;C9 = 220p; 40 V Cio;Ci5 = 10p: 16 V Ci2;Ci4;Cie. . .Ci8 incl.;C27= lOOn C25;C26 = 47p polystyrene/styroflex C28. . .C31 incl. = 22n Semiconductors: Bi = B80C1500 (80 V; 1.5 A bridge rectifie (Universal Semiconductor Devices: C-l Elei Ironies) Di . . .D13 incl. = 1N4148 Du. . .D23 incl. = 3 mm LED in Si . . .Sic (ITW switch) Ti;T2 = BC547B ICi =401 1 1C2 = 4013 IC3;IC4 = 4028 ICs=ULN2804A (Spraguel IC6,IC7=OP-227GY (PMI) or OP-227GN/GJ (Linear Technology) IC8=7812 IC8=LM325N K2= 3-way PCB terminal block. K3= 20-way male PCB header. One 20-way female Rateable connector (IDC type). Two 10-way female Rateable connectors (IDC typel. Approx. 15 cm of 20-way flat ribbon cable, or two lengths of 10-way cable. Fig. 9. Component layout of the power supply board. References: 111 Top-of-the-range Preamplifier — Elektor India, Dec. 1986, Jan/Feb 1987. Fig. 12. Foil for Ihc front panel. When the preamplifier is switched on, fier by eight screws. This number of the decoders are automatically set to 0, screws is necessary to spread the mech- becausc their inputs are connected to anical load evenly over the boards, ground (=0) via resistors. In this state The component mounting plan for the the decoder will remain inactive until control and amplifier board is shown in one of the switches is pressed. If it is Fig. 9. desired that one of the inputs is active on Note that switches Si to Sio must have switch-on, a 100 n capacitor should be two terminals for the mother contact, connected across the relevant switch. because the connection between these two serves as a wire link in some of the switches. The board provides three common ter- minals per channel for the volume and balance controls. The connections be- tween these controls must therefore be hard-wired. Always begin work on PCBs with placing the required wire links: these are easily forgotten once the board has been populated. Note that header K3 and the 1 pF polycarbonate (polyproylene) capacitors should be fitted at the track side of the board. In some cases, it may also be ad- vantageous to locate solder pins at the track side. Any wiring carrying audio signals is best made in single screened audio cable. The screens may be earthed at both sides, since the boards have been designed to prevent earth loops. Construction The two bus boards are mounted one above the other at a distance of about 20 mm. This ensures that terminals A to N incl. are opposite one another, which - facilitates inter-wiring them. The component population plan of the two boards is shown in Fig. 6 and Fig. 8. To facilitate the interconnection of ter- ^ minals A to N, soldering pins should be ■ Jfc used on bus board 1 at the 14 positions ■ (M fk indicated. These pins should, of course, ^ ^ ™ be put in place before the resistors of the input potential dividers are mounted. On bus board 2, solder a short length of Fig. 13. Flat cable connecting the control wire to terminals A to N. These lengths board to the two bus boards, of wire are later soldered to the corre- sponding soldering pins on board 1. Connections between the control-board Before the two boards are finally con- and the relays on the bus boards are nected together, solder appropriate made by a short length of 20-way flat lengths of wire to terminals VR and VL cable — see Fig. 13. One end of the cable on bus board 1: these points are difficult is terminated into a 20-way connector to get at after the sandwich has been and the other end into two 10-way con- formed. nectors. Once the two boards have been made Finally, all identically named terminals bus boards are into a sandwich, they may be mounted on the power supply board and the con- to the inside rear panel of the preampli- trol board should be interconnected. Power supply The circuit of the power supply is shown in Fig. 5. The supply for the control cir- cuits and the relays is stabilized by ICe, a Type 7812 that has been ‘elevated’ to a 12.7-V regulator with the aid of Ds. This is done to compensate the voltage drop across the outputs of ICs, so that the full 12 V remains available for the relays. The symmetrical supply for the buffer- amplifier is regulated by ICs>. Any mains noise is filtered by capacitors shunting the diodes of bridge rectifier Bi. All parts of the power supply, except the mains on-off switch and Ki, are housed on the PCB shown in Fig. 10. Fig. 10. Component layout of the control ULTRASONIC DISTANCE METER Until well into the twentieth century, most devices developed for measuring distance worked on the same principle: comparison of the measured distance with a standard unit of length Other means are now available. One of these is the measurement of time taken by a sound wave to cover a certain distance. This sound normally lies beyond human hearing. The ultrasonic rangefinder presented here is suitable for measuring distances between 25 cm and about 6 m. The measured distance is shown on a 3-digit liquid crystal display— LCD. The low current drawn by the unit makes battery operation possible: a ‘LO BAT’ reading on the LCD indicates when the battery needs to be replaced. The block schematic in Fig. 1 shows the four major parts of the meter: a sender, a receiver, a timing and time reference section, and a counter with display. The transduction element emits bursts of 12 pulses at a frequency of about 40 kHz. This frequency is roughly ident- ical with the resonance frequency of the two transducers, so that some sort of selectivity is obtained at the sensing el- ement. As soon as the first burst is emit- ted, a bistable is actuated which enables the counter. Immediately after the burst has been emitted, the unit is switched to recep- tion. The sensitivity of the receiver is a function of time. During and immedi- ately after emission of the burst, the sen- sitivity is low. Crosstalk between the transduction and sensing elements has, therefore, no effect on the operation of the unit — see Fig. 5. If an echo is re- ceived very soon after cessation of the emitted burst, it will be sufficiently strong to be processed by the receiver in spite of the very low sensitivity. An echo that takes a longer time to reach the sensing element will be weaker, but by then the sensitivity of the reciever has be- come higher. The upshot of this arrange- ment is that reliable measurements, unaffected by spurious reflections and crosstalk, may be made with relatively simple means. At the instant the echo is sensed, the bistable is reset and the counter state transferred to the output latch. Since the clock frequency is 17.05 kHz and the velocity of sound under normal atmospheric conditions may be taken as 341 m s~', the period of the clock is equal to the time taken by the burst to travel 2 cm i.e., 1 cm forward and 1 cm back. This means that the number of clock pulses counted between the onset of emission of the burst and the sensing 11. 44 eleklor India November 1988 of the echo is equal to the number of centimetres between the transducers and the reflecting surface. Accuracy The accuracy of the measurement depends on the precision with which time is measured and on the ambient conditions. The speed of sound depends on the atmospheric pressure, the tem- perature, and the air density. Readers in- terested in the details of these dependen- cies are referred to the inset box. A source of larger errors than caused by atmospheric conditions is the unit itself, mainly due to the incorrect triggering of the receiver. Partly because of the Q fac- tor of the sensing element, it takes a finite time (up to a few periods of the 40 kHz signal) before the received signal attains maximum amplitude and the re- ceiver is triggered. Each delayed period causes a measuring error of about half a centimetre. None the less, under normal conditions, measurements made with the prototype at up to 6 m were at all times accurate to within 2%, i.e. 2 cm per metre. Circuit description The transduction element is driven by four paired CMOS buffers. The output stage is actually a full bridge which causes a doubling of the effective voltage across the element. Capacitor Ci blocks the DC component of the output signal during pauses in emission. To obtain bursts at maximum energy, ICi is con- nected direct to the 9-volt battery. The remainder of the circuit operates from 5 V. The 40 kHz oscillator is tuned to the resonance frequency of the transducers with the aid of Pi. The regulated supply voltage ensures adequate frequency stab- ility. Comparator A 6 matches the logic levels of the oscillator (high = 5 V) and the output circuit (high =9 V). The 5-volt supply is regulated by a 78L05. This type of regulator requires only a small bias current at low output currents and thus helps to keep the overall current drawn by the circuit low (typ. 4.5 mA). Unfortunately, the load regulation of this regulator is poor: good decoupling, praticularly of the counter IC (Ri9-Cu), is therefore essential. Fig. I. Block schematic of the distance meter. The central timing is provided by IC4. When Si is pressed, output Q12 goes high twice a second. Network R2-C11 enables the 40 kHz oscillator for about 0.3 ms, so that the emitted burst con- tains 12 periods of the 40 kHz signal. During emission, the output of Ai is high which, via Di, causes the threshold of comparator As to be raised to a level that makes triggering by crosstalk im- possible. At the start of an emission, bistable N«- N10 is set. This disables the count in- hibit input of ICk, which thereupon commences counting the 17.05 kHz pulses applied to pin 32 by ICa. Receiver input amplifier As has a gain of 33 dB [20 log(R8/R9)J. The amplifier is AC coupled, because the sensing el- ement has a virtually infinitely high DC resistance. The input offset voltage is, therefore, not amplified. Also, Rm serves to minimize the offset voltage caused by the input bias current. A minimum offset voltage at the output is important because, together with the in- put offset voltage of As, it determines the maximum attainable sensitivity. Time-dependent sensitivity is realized by Ai lowering of the trigger level of As via time constant R<,-C«. The maximum sensitivity may be matched to the am- bient conditions by P.<: more about this under calibration. When an echo is received, the output of As goes low, which causes the bistable to be reset, and this in turn disables the clock to ICs. At the same time, a short negative pulse is appli ed via R13-C12 and N11 to pin 34 (STORE), which results in the transfer of the counter state to the output latch of ICs. Gate N11 merely buffers the low-impedance store input. When the Q12 output of IC4 goes low, the counter in ICs is reset, and the cir- cuit is ready for the next measurement. If Q12 goes low in the absence of an echo, the counter is still reset, as is the bistable (via D.i). The display then reads 0.00 to indicate an abortive measure- Apart front a counter, ICs also contains all the necessary circuitry for driving a 3 '/2-digit display. Only three digits arc used in the present circuit. Gate N12 in- verts the backplane signal of the LCD and thus provides a fixed drive for the decimal point. The battery voltage is monitored by Nu. When it drops to about 7 V, the gate’s function changes from non-inverting to inverting, which causes the LO BAT seg- ment of the LCD to light. Flickering of this is prevented by the hysteresis of around 200 mV provided by Ris. Construction Before anything else, make sure that the printed-circuit board fits snugly in the chosen case. Note that two corners must be removed to allow passage of the Velocity of sound In a gas The velocity of sound, v, in a gas, such as air, for frequencies above 200 Hz, is given by v=4p'e> r Is the adiabatic bulk modulus of the gas (1.4 for air) p Is the pressure of the gas In Pa (air pressure at sea level Is 1.01325x10* Pa) e Is the density of the gas In kg m' 3 (density of alr=1.29 kg nr 3 ) If a mole of air has a mass M and a volume V, the density Is M/V and the velocity of sound, v, is v= ftrple)= \\ipV/M) But pV=RT, where R is the molar gas constant and T is the absolute tem- perature Therefore, v=\ ! (yRT/M) Since 1 . M and R are constants for a given ga* it follows that the velocity of sound in a gas is independent of the pressure If the temperature remains constant. It also follows that the velocity of sound is proportional to the square root of its absolute temperature. Thus, If the velocity in air at 0 °C is 331 m s' 1 , the velocity at room temperature, 20 °C=293 K, Is calculated from W331= ^(293/2731=331 11. 07326= 342.91 m s' 1 Fig. 3. General view of the distance meter. screws that fasten the front and rear of the case. Many wire links are required and these should, as a general rule, be soldered in place before any population of the board takes place. Make sure that the LCD is mounted at the correct height to fit snugly in the window provided in the case. The distance between the top of the display and the board must be 25 mm. To prevent crosstalk of the LCD drive pulses to the receiver, it is essential to fit a tin or brass screen between the upper row of LCD pins and the transducers. This screen is fitted between the two solder pins provided. A second screen is required to cover the shaded area in Fig. 4. It should be soldered to the first screen near Co, and kept in place with the aid of a few drops of superglue or epoxy resin. The tranducers may be fitted on to the solder pins provided on the board or outside the case, for instance, in the bumpers of a car. On the board, they wil be located towards the front of the case, in which two 16 mm dia. holes must be drilled. If mounted externally, they are connected to the board by 2-way in- dividually screened cable. If the unit is used in a car, and supplied from the car battery, it is advisable to connect a small choke in series with the supply line to the meter and decouple it with a 100 pF, 16 V capacitor. Calibration A good multimeter is essential; an os- cilloscope and/or frequency meter is useful. First, the frequency of the 40 kHz oscil- lator must be matched to the resonance frequency of the transducers. Connect a temporary wire link between pins 1 and 14 of IC2: this will cause the transduc- tion element to operate continuously. Turn Pi fully anticlockwise. Measure the current drawn from the battery with the multimeter and turn Pi slowly clockwise until the current is a maxi- mum (about 16 rnA). The oscillator is then set to the correct frequency. Note that when Pi is turned further, there is a second current peak, but thal is NOT the required point. This is all assuming thal the 4093 used in the IC2 position is of SGS or RCA manufacture. The Motorola version has a smaller hysteresis and this may necessitate an increase in the value of C2 to 2n2. The National Semiconductor version, on the other hand, has a higher hysteresis, so that the value of C2 may have to be reduced to 470 p. Remove the wire link from pins 1 and 14 of IC2. Press Si and make sure that the transduction element produces a short click twice a second. Next, P2 must be adjusted until the os- cillator in IC4 operates at 17.05 kHz 11.46 Parts list Resistors l±5%): Rl = 27K R2;Ria = 180K R3 = 10K R4;Rb;R7;Rb;Ri3. . .Rib incl.;KR20-100K Rb;Rb=2K2 RlO=47K Rtl = 18K R12-220K Rl7 = 39K Ria-IMO RI9-1K0 Pi = 28K multiturn preset P2=10K preset V P3 = 1M0 preset H Capacitors: Ct;Ce-220n C2-1nO (see text! C3=10p: 16 V; tantalum C4. . .C7 incl.:Cs = lOOn CtO=1nO Cli =5n6 Cl2=270p Ci3=1pO: 6.3 V; tantalum Ci4=15p Semiconductors: D1...D4 incl. = 1N4148 1C 1=4049 IC2=4093 Isee text) IC3=78L05 IC4=4060 IC5=LM324 ICe=4030 IC7=LM393 ICe=ICM7224 . . , Miscellaneous: Ui=MA40A5S ultrasonic transmitter IMurata'I U2=MA40A5R ultrasonic receiver IMurata *1. 3 'A -digit LC display with LO-BAT indication. Si = push-to-make button. S2= miniature SPDT switch. 2 off 20-way contact strips for mounting LC display. Hand held ABS enclosure: e.g. BICC-Vero Type 65-2996H (BICC-Vero Electronics Limited e Parr e St. Helens e Merseyside WA9 1PR. Tel.: (07441 240001. Alternative type: W81 '. Press-on clip for 9 V PP3 battery. PCB Type 880144 . ! 'Listed by ElectroValue Limited e 28 St Judes Road e Englefield Green e Egham e Surrey TW20 OHB. Telephone: (0784) 33603. Telex: 264475. Northern branch: 680 Burnage Lane e Manchester M19 1NA. Telephone: 1061 432) 4945. 1 Murata Electronics (UK) Limited e 6 Armstrong Mall • Southwood e FARNBOROUGH GU14 ONR. Tel.: (0252) 523232. Telex: 858971. Fax: (0252) 511528. (measured with a frequency meter at pin 9 of the IC). In the absence of a fre- quency meter, place the unit in a pos- ition where the distance between the front of the transducers and a good reflecting surface (a wall or window pane) is exactly one metre (measured with a tape rule or similar). Press Si and turn Pi until the display reads 1.00. If the reading is not stable or just 0.00, turn P3 slightly until a correct, stable reading is obtained. Adjustment of Pj (sensitivity) depends largely on the circumstances of use. In quiet surroundings, the control may be set fully anticlockwise (maximum sensi- tivity). If, however, the display gives spurious readings, like 128, 256, or 512, the sensitivity is too high: the meter then detects its own clock. This is obviated by turning Ps slightly clockwise. If the unit is used in noisy surroundings, reduce its sensitivity even further, so that it does not respond to spurious sounds. Note, however, that the maximum measureable distance is then reduced. It should be borne in mind that absorb- ent surfaces, such as furniture, dressed people, and so on can not, or at least not reliably, be detected. This is because the echo from them is too weak to trigger the receiver. It pays, however, to experi- ment. For instance, the sensitivity of the receiver may be increased (within reason) by reducing the value of R<>. Further- more, the time dependency of the sensi- tivity may be altered by changing the value of time constant Re-Cs. Reducing that value makes the meter more sensi- tive over shorter distances. MACROVISION DECODER/BLANKER First used by CBS-Fox on PAL VHS tapes of the action movie Crocodile Dundee , the MacroVision encryption system is gradually being introduced by film and video rental companies to prevent customers making copies of prerecorded video tapes. This article describes the basic operation of the MacroVision system, and proposes a circuit that negates the copy protection signal. Invisible lines In the PAL system, a television picture is transmitted (and recorded) as 625 in- terlaced lines. Actually, the picture, or frame, is transmitted as two rasters of 312.5 lines, at a speed of 25 per second (50 rasters per second: the field fre- quency is 50 Hz). Not all lines are, how- ever, visible on the screen. The vertical blanking interval (VBI) comprises the vertical (raster) synchronization pulse, and about 17 blank lines, which produce a black bar at the top of the screen when the picture is shifted downwards with the vertical picture position control. Most TV stations, however, use the 17 lines in the VBI for broadcasting Teletext and/or timing signals for VCRs. On many video tapes, the blanking interval is used for storing coded product registration data and title labels, which can be read back with the aid of special, proprietary, equipment. Not surprisingly, the MacroVision system also makes use of the available lines in the VBI. Upsetting the AGC On the latest releases of MacroVision en- coded video tapes, the contents of lines 5 up to and including 14 following the raster sync pulse contain pulses that in- tended are to upset the operation of the VCR’s recording circuits. This is achieved as outlined below. The amplitude of the colour CVBS (composite video blanking synchronis- ation) signal provided by VCRs is stan- dardized at 1 V PP at a load impedance of 75 Q. The highest and lowest instan- taneous amplitude of the output signal corresponds to maximum intensity (white) and minimum intensity (bottom of sync pulse) respectively. The black level is usually slightly higher than the top of the sync pulse at an amplitude of 0.3 V. Virtually all VCRs have a built-in auto- matic gain control circuit (AGC) at the input to optimize the signal-to-noise ratio by making sure that the recording amplifier is driven with the standard signal amplitude. Most of these AGC circuits are capable of correcting input amplitudes between 0.5 V PP and 2 V PP , and it is precisely this characteristic that is ‘exploited’ by the MacroVision system. Figures la, lb and lc show a number of picture lines with different contents. Fig. la is the reference, showing the well- known staircase test signal. The line starts with the line synchronisation pulse, followed by the so-called rear porch, which serves as the black refer- ence (in a colour signal, it also carries the colour burst). Then follows the actual picture contents, represented here as the staircase (compare this to Fig. lb, which shows a blank line). The MacroVi- sion signal is shown in Fig. lc. It is com- posed of 5 black-to-white transitions at a frequency of about 48 kHz, with ‘black’ going lower than the reference level, and reaching down to the bottom of the sync pulse, while ‘white’ has about two times the amplitude of the standard white level. It will be clear that almost any AGC will fail to correct the amplitude of such a signal, whose in- terfering effect is further boosted by variation of the maximum white level. The AGC circuits in most VCRs use the sync pulse as the reference for setting the amplitude of the video signal. The rear porch level is measured with respect to the bottom of the sync pulse, and set to about 0.3 V, In the lines affected by a MacroVision anti-copy burst, the lowest level of the signal equals that of the sync bottom, causing the recording VCR to mistake these levels for sync pulses. This, in turn, causes the AGC to set the input amplifier gain on the basis of the next black level, which is not a black level at all, but a maximum white level. The AGC can not but reduce the signal am- plitude to such an extent that the picture becomes dark, and difficult to synchron- ise properly. The ultra-white level of the MacroVision may also wreak havoc with A prototype of the MacroVision decoder/blanker housed in an ABS enclosure. Fig. 1. Staircase test signal (la), blanked line (lb) and MacroVision interference signal (lc). Fig. 2. Double-trace oscillogram showing a line with MacroVision interference (upper trace), and a normal, empty line in the blanking interval (lower trace). the AGC’s overdrive protection, reduc- ing the signal amplitude even further. Not always effective? The degree of interference caused by the MacroVision anti-copy burst in the VBI varies from VCR to VCR. In addition to this fact, it is noteworthy that the burst appears to affect VCR input circuits only, not those of most TV sets. It will be clear from the above discussion that the effect of the interference caused by the MacroVision bursts depends mainly on the dynamic behaviour of the AGC circuit in the VCR. This behaviour, in turn, is defined by the regulation time constants of the circuit. Some VCRs have a ‘fast-acting’ AGC, others a rela- tively ‘slow’ circuit. The latter types are largely insensitive to the pulses in the VBI, and can be used for copying tapes even if these are MacroVision-protected. Modern TV sets generally do not suffer from instability caused by MacroVision- coded signals because the operation of the internal, PLL-controlled, line sync generator is usually not affected by the interfering pulses — hence, the reference black level is correctly deduced from the input signal. Also, there is no input over- drive protection circuit that controls the AGC — signal levels exceeding maxi- mum white are simply clipped. MacroVision decoder/blanker The task of the decoder/blanker is to recognize the MacroVision anti-copy burst in 10 successive lines in the VBI, and replace it with a blank (black) level, hence the name decoder/blanker. Rela- tively simple to formulate, this task is not at all simple to carry out in practice. The circuit proposed here is fairly com- plex because it was purposely designed around discrete, commonly available, components rather than (expensive) special ICs. The operation of the decoder/blanker is explained with reference to the block diagram of Fig. 3 and the circuit diagram of Fig. 4. At the input of the circuit, Ti and Ta form a buffer with an amplification of 2. The signal is then clamped by Di, so that comparator IC2 (a BiMos opamp Type CA3130) can filter out the line (H) and raster (V) synchronisation pulses. The line pulses control ESi after being filtered in C5-L2- Ts. Similarly, the raster pulses reach T<> after passing through an L-C low-pass filter. The raster pulses at the start of the blanking interval serve to define the time slot available for ‘capturing’ the MacroVision signal. The positive edge of the raster pulse triggers monostable MMV1, which introduces a delay of 300 p s to time the fourth line, at which the interference starts (see Fig. 5). After the delay has lapsed, MMV2 is trig- gered. Its output controls electronic switches ESi, ES 2 and ES 3 . During the MacroVision burst, ES 2 breaks the video signal, while ESi feeds the black level obtained with potential divider R7- R* to output buffer T3-T4. The line synchronisation pulses required during the blank lines are provided by Ts via ESj pulling the gate of T 3 to ground. MMV 2 is dimensioned for a monotime of 589 ps, covering the duration of 9 of the 10 Macrovision lines. After having filled these with a continuous black level, ES 2 again passes the normal video signal, until the decoder is re-triggered. Note that it is not possible to blank out exactly 640 ps (10 lines), because this would give rise to colour purity errors near the top edge of the picture. In some cases, the MacroVision system also af- fects the colour burst. The status indication LEDs of the decoder/blanker obviate the need for an oscilloscope for a quick check whether or not a particular tape is MacroVision- coded. When a correct video signal is applied to the decoder/blanker, the LEDs for horizontal and vertical sync will light steadily, while LED protected tape flickers when the MacroVision signal is recognized. The output buffer of the decoder/blanker can drive two 75 Q loads. The input amplifier of the circuit should be driven from a 75 Q source at an amplitude of 1 Vpp (an external pre- amplifier or attenuator may be required to ensure this level). No alignment required The construction of the MacroVision decoder/blanker on the printed circuit board shown in Fig. 6 is straightforward and requires no further discussion other than that it is important not to overlook the six wire links. No alignment should be required when the relevant 1% resistors and close- tolerance polystyrene capacitors are used as stated in the parts list. The monotime of MMVi and that of MMV 2 are pur- posely made slighty longer and shorter respectively to compensate tolerances. Fig. 4. The low-cost MacroVision decoder/blanker has no adjustment points, and is con- When the capacitors and resistors in the structed entirely with discrete components. delay circuits have a tolerance greater 11.50 Fig. S. About 300 ps after the vertical synchronisation pulse, the decoder circuit uses a lime slot of 585 ps to replace the interfering pulses in 9 of the 10 MacroVision lines with a steady- black level. than 5%, some MacroVision interference may gel through to the recording VCR because ES2 either shuts down too late', or passes the video signal too early. In this case, R30 and Rsi may be made ad- justable (use 10-turn presets) to enable accurate adjustment of the delay times. It is possible to use a 74HC4066 instead of the 74HCT4066 in position ICi. A LOCMOS type HEF4066 should also work, but this was not tested in practice. TRANSISTOR CURVE TRACER There exist many ways of testing transistors, but each of these has its limitations because only one parameter is tested at a time. The curve tracer presented here tests all major characteristics in one go by displaying a number of curves on an oscilloscope screen. One limitation of the tracer should be mentioned right from the start, however: in the version discussed here, it can only test n-p-n transistors. Background »o transistor testing A simple o.k./faulty test of a transistor can be carried out by considering the device as consisting of two anti-series connected diodes (Fig. 1). This test, which can be carried out with the aid of an ohmmeter, is fine for an initial check, but fails to provide information on one of the most important transistor characteristics: the static forward current transfer ratio, hpi:, also referred to as the current amplification. Most bipolar transistors have 3 ter- minals: base (B), emitter (E) and collec- tor (C). For the description of their elec- trical characteristics, however, tran- sistors are often treated as four-pole cir- cuits. This is so because one terminal, usually the emitter, is common to the in- put and the output (Fig. 2; common emitter circuit). The four-pole circuit of Fig. 2 thus has 2 inputs, base and emit- ter, and two outputs, collector and emit- ter. Electrically, there are four important parameters to consider: base input cur- rent (Ib), input voltage (Ube), output collector current (Ic), and output voltage (Ucu). Without going into the actual, quite complex, operation of the transistor, it is safe to say that this should convert a base current into a more or less propor- tionally larger collector current. The conversion ratio is the previously men- tioned static characteristic Iife, some- times also written as a’. Figure 3a shows that the collector cur- supply voltage level, because it is con- rent is hre times greater than the base trolled solely by the base current. The current. The base input voltage is largely circuit thus obtained is called a current constant at 0.6 to 0.7 V (this is the for- source. ward drop across the base-emitter di- Output voltage rather than output cur- ode), while the output voltage is deter- rent is obtained by inserting a series re- mined by the way the collector is conncc- sistor in the collector line as shown in ted. The collector may be connected Fig. 3b. This resistor of value R direct to the positive supply rail, making translates the collector current into a col- the collector current independent of the lector voltage, and the circuit thus forms The simplest way of testing transistors is the ohm- li-series connected diodes. transistor is essentially formed by r---