54 October 1987 INDIA SINGLE-CHIP MICROCONTROLLERS 87 WORLD CUP CRICKET ON PAGE NO. 1081 POCKET IT! EPROM emulator Filters : theory & practice l/BISA V ri r Y-i'j 4 V \ 9 3 r .9 \ j* 1 Publisher: C.R. Chand arena Editor: Surendra Iyer Technical Editor : Ashok Dongre Circulation: J. Dhas Advertising: B.M. Mehta Production: C N Mithagari Address: ELEKTOR ELECTRONICS PVT. LTD 52, C Proctor Road. Bombay-400 007 INDIA Telex (Oil) 76661 ELEK IN Overseas editions: Elektor Electronics 1. Harlequin Avenue. Volume-5 Number-10 October-1 987 Great West Road, Brentford TW8. 9EW | U K Editor Len Seymour Electronics Technology Pulitron PubUcacoes Tecnicaa Ltda Av Ipiranga 1 100. 9° andar CEP01040 Sao Paulo Brazil Editor: Juliano Barsali Elektor sari Route Nationale. Le Seau. BP 53 592270 Bailleul - France Editors: D R S Meyer: G C P Raedersdorf Single chip micro controllers 10-22 Testing the instruments of tomorrow 10-26 Stream encryption 10-28 Elektor Verlag GmbH Susterfeld-StraBe 25 100 Aachen — West Germany Editor: E J A Krempelsauer Elektor EPE Karaiskaki 14 16673 Voula Athens - Greece Editor: E Xanthoulis Measurement of ventricular distances 10-31 A tidal generator for energy and jobs 10-34 Filters: theory & practice Part-2 10-36 Elektor BV Peter Treckpoelstraat 2 4 6191 VK Beek — the Netherlands Edrtor P E L Kersemakers Ferreira & Bento Lda R D Estefama 32 1° 1000 Lisboa — Portugal Editor: Jorge Goncatves Ingelek S.A. Plaza Republics Ecuador 2 28016 Madnd-Spair Editor: A M Ferrer Projects Universal EPROM emulator 10-41 Active phase-linear cross-over network 10-48 In Part: Kedhorn Holdings PTY Ltd Cnr Fox Valley Road & Kiogle Street Wahroonga NSW 2076 - Australia Editor: Roger Harrison Headlight alarm 10-52 16 Kbyte CMOS RAM for C64 10-53 Electronic Press AB Box 63 182 11 Oanderyd - Sweeden Editor: Bill Cedrum Information The Circuits are for domestic use only The submission of designs of articles of Elektor India implies permission to the publisher to alter and translate the text and designed and to use the contents m other Elektor publications and activities The publishers cannot guarantee to return any material submitted to them All drawings, photographs, printed circuit boards and articles published in Elektor India are copyright and may not be reproduced or imitated m whole or part without prior written permission of the publishers Patent protection may exist in repect of circuits, devices, components etc described in this magazine The publishers do not accept resonsibility for failing to identify such patent or other protection MEMBER Printed at : Trupti Offset: Bombay - 400 013 Ph 4923261, 4921354 Copyright © 1987 Elektuur B.V. The Netherlands Telecommunication News 10-18 Electronics News 10-20 New Products 10-64 Datalek 10-75 Guide lines Switchboard 10-71 Classified ads 10-80 Index of advertisers 10-80 Datasheet 10-81 Selex-27 Time-Lapse Photography 10-56 Universal Power Supply 10-59 eMtor lod.s octotwr 1987 1 0-05 TELECOMMUNICATIONS NEWS • TELEC FIRST COMPUTERIZED BUREAU SYSTEM FOR SATELLITE TRUCK Texas Television Station WFAA has become the first news station to equip its satellite truck with the Bureau System produced by BASTS Inter- national, a subsidiary of In- dependent Television News— ITN. The installation gives WFAA I remote newsroom capabilities directly tied to the news pro- duction system by linking the station’s DalSat electronic news gathering (ENG) truck to the BASYS system at headquarters. BASYS systems are already used by over 100 radio and television newsrooms worldwide, includ- ing Cable News Network, the National Broadcasting Corpor- ation, the American Broad- casting Company, the British Broadcasting Corporation, and ITN, but WFAA is the first to im- plement the remote newsroom system. (LPS) NEWSROOM SYSTEM FOR SWISS RADIO INTERNATIONAL BASYS International has re- ceived an order from Swiss Radio International for the supply of a newsroom com- puter system capable of deal- ing with the many languages used by SRI. The system will allow SRI jour- nalists to view the four different languages in which they take copy, write in all the Roman alphabet languages they use, and also print them. BASYS has also developed a method by which material generated in the main newsroom can be downloaded to separate personal com- puters, allowing Arabic jour- nalists and translators a bi- character environment. This means that virtually all SRI's 24-hour-a-day broadcasts in seven major languages (English, French, German, Italian, Portuguese, Spanish, and Arabic) plus either Ro- mansch or Esperanto, can be computerized. Similar BASYS systems are already being used by YLE in Finland and by the BBC. (LPS) Hi-fi VCR from Mitsubishi Mitsubishi Electric Corporation recently put on the market a new hi-fi VCR whose picture quality almost matches that of one-inch professional equip- ment. The new unit retails at Y218.000 (about $1,4S0). The company plans to produce 5,000 units per month. SATELLITE COM- MUNICATIONS FOR THE CONSUMER MOVES CLOSER The International Maritime Sat- ellite Organization (INMARSAT) has issued final specifications for its Standard-C satellite com- munications system. INMARSAT is the 48-country in- ternational consortium that operates a system of nine satellites worldwide for the pro- vision of maritime and other mobile communications ser- vices. Main features of the Standard-C system are that it uses very small earth stations weighing only a few kilograms to transmit and receive telex, electronics mail or data to or from practi- cally anywhere in the world, regardless of distance or weather and independent of existing communications fa- cilities. The "C” in Standard-C could stand for consumer be- cause, for the first time, it will give the consumer access to the quality and reliability of sat- ellite communications. Demonstrations of the Standard- C system would begin during the latter part of this year; sea trials would be held in early 1988, and full service should be available through some coast earth stations during the sec- ond half of next year. (LPS) NEW LIFE- SAVING RESCUEPAGERS FOR RNLI The Royal National Lifeboat Institution— RNLI— the charity which operates rescue services around the British coastline, is to have a tailor-made communi- cations system that will mean faster call-out for its lifeboats. The Rescuepage system has been devised by British Telecom Mobile Communi- cations (BTMC) and will replace such traditional call-out devices as explosive Dares. The first batch of 1000— out of a total of 2000— specially adapted Radiopagers is already being delivered to lifeboat stations that at present are hampered by poor communications or cum- bersome call-out procedures. The new procedure will enable an entire crew to be called out through a single telephone call which alerts all their BT Tone Radiopagers. (LPS) EURO CELLULAR RADIO Now that France and Federal Germany have agreed to the narrow-band standard for a Pan- European cellular radio system set by the Conference of European Posts and Telecom- munications earlier this year, the Department of Trade and In- dustry has given the go-ahead for a £1 million cellular radio project. The project, involving British Telecom, Racal, GEC, and Plessey, is expected to produce results by the end of the year. Two operators, Cellnet and Racal-Vodafone, have been allocated space in the proto- type spectrum for testing proto- type Pan-European radio equipment and systems. In the wake of all this activity. Plessey and Racal announced the setting up of Orbitel Mobile Communications, owned equally by them, who will de- velop infrastructure equipment and mobile radiotelephones for the European system. The new company, whose workforce is expected to reach 300 by the end of the year, will be headed by Mike Pinches, until his appointment technical director of Racal Telecommuni- cations. (LPS) TELETEXT SPREADS ITS WINGS FURTHER STILL Logica has won a further con- tract from the Swiss Teletext Corporation to extend its Pavane teletext editorial system at Biel. Believed to be already the largest system of its kind in the world, Pavane provides a full teletext and subtitling ser- vice in French, German and Italian. This will be the second Logica teletext system for the Swiss Teletext Corporation. The first accepts data from Telekurs, a financial services information provider. Logica’s work on teletext began ten years ago in conjunction with the BBC’s CEEFAX ser- vice. Since then, Logica has supplied teletext systems to Australia, Austria, Canada, Finland, Germany, Italy, New Zealand, Singapore, Switzer- land, and the United States.(LPS) 10-18 •lefctor india October 1 987 TELECOMMUNICATIONS NEWS • TELEC Life saving communi- cations system Cut down the time between re- ceiving an alarm call and taking emergency action: that is the requirement of a new alarm centre communication system now under test in Sweden. After only a short period of (test) use, the system has already shown that the time between the alarm call and consequent action can be reduced appreciably. The system, called Coordcom, integrates and co-ordinates in- formation support and com- munications handling for alarm centre operators. It has been developed by a subsidiary of Swedish Telecom arid will be shown at Telecom '87 in Geneva from 20 to 27 October. DOUBLE FIRST FOR RACAL AVIONICS Alaska Airlines of Seattle is the first US air carrier to purchase the Racal Avionics advanced RNS5000 navigation manage- ment system. Racal will provide 19 of the systems for Alaska’s Boeing 727 fleet at a cost of £750,000. The contract is a double first for the British company because, for the first time, the RNS5000 will be used with an inertial ref- erence system (IRS) and a head- up guidance system (HGS). The secret of the RNSSOOO's high navigational accuracy lies in its ability to process data sim- ultaneously from a number of different navigation sensors, any of which may be selected to ’’steer by”. More accurate air- ways by flying on precise go- direct guidance lead to an overall reduction in route mileage with a corresponding saving in operating costs. ESTEC contract for Signal Processors The European Satellite Tech- nology Centre— ESTEC— has awarded a contract to Signal Processors of Cambridge for a study on the application of a novel technique invented by SPL to improve sensitivity of ground receivers used to track satellites. The work will be earned out in collaboration with the SERC’s Rutherford Appleton Labora- tory which funded the initial work by SPL to validate the new technical approach. Its first ap- plication is likely to be in ex- periments by the European Space Agency with the Olym- pus satellite, due for launch in 1989, which will operate at much higher frequencies than are employed in current satel- lite communications. SPL's approach avoids the use of phase-locked loop signal recovery methods in the receivers. Instead, it exploits digital signal processing by the use of fast Fourier Transform techniques. This is expected to have the additional benefit of lower manufacturing costs. BOOST FOR CITY TELECOM- MUNICATIONS British Telecom is to spend a further £40 million on optical fibre links for its- business customers in the City of London. In a major step towards com- pletion of the new system, STC Telecommunications, with Plessey as sub-contractor, has been awarded the contract for the second phase of British Telecom’s City Fibre Network (CFN), enabling customers to channel all their services through a single "pipeline”. The first phase of the project, announced last December, is nearing completion. Under this £30 million contract, more than 60,000 km of fibre has already been installed, representing the bulk of the CFN cabling. CABLE TECH- NOLOGY FIGHTING BACK According to Cable Hardware & Technology Market in the US (#1653), a study just published completed by Frost & Sullivan, the VCR has been entirely responsible for the drop in cable operator’s revenues from pay services. The report notes that the very effective competi- tion of the VCR has forced operators to increase exper- iments with pay-as-you-view programming, suggesting major growth areas in ad- dressable home converters and in computer systems for billing, tracking, and servicing cus- tomers. Overall, the study says, capital expenditure by the cable oper- ators should grow about 5% a year through 1990, from the $1.5 billion that was spent on equipment in 1986. About 6,500 cable systems now serve 40 million subscribers; F&S believes the 71,100 miles of plant construction done in 1986 will stand at 74,500 miles in 1990. However, the proportions of new vs replacement plant construction will shift dra- matically: new wiring was 55% of the 1986 mileage put in, but will be little more than a tenth of the 1990 figure. CABLE INVESTMENT PER MILE $ T h o u s a n d s 5 i - fia ill SI 4 I i 3 ] 2 lr i i LH o 1 984 1 985 ‘ 1 986 1 987 1 988 1 989 1 990 ‘ 1991 Year elefcior incha October 1967 1 0* 1 9 ELECTRONICS NEWS • ELECTRONICS N1 RIBBON INDUSTRY Computers and electronic typewriters may have varying market but the market for typewriter ribbons is constantly growing. According to conservative estimates, there were 40,000 computers and 20,000 electronic typewriters in India by the end of 1 986 and in 1987, another 25,000 computers and 20,000 electronic typewriters are expected to be added. Assuming a consumption of two ribbons per installation per month, the annual market for ribbons is estimated at Rs.50 crores and this is likely to grow to Rs.1 50 crores per annum by 1990. Different cassette manufacturers have different designs for the same model. The length of the fabric specified by manufacturers is different depending on the design. The internal mechanism also differs from type to type. Different printers produce different impacts and a proper combination of ink and fabric is essential to achieve the same darkness of print. Often the thickness and width of fabric may be same for two different ribbons but the ink formulation in them will be different. This aspect is often ignored by customers. Most of the computer ribbons currently in use are endless type with a joint in the fabric. The joint should be strong and smooth, as the rough joint will damage the print mechanism. Ultrasonic weld process is widely used all over the world for this joint but results of joints by this process are not satisfactory. The Japanese have eliminated the joint in some of the new ribbons by using a woven circular loop. In India, Ink-Link India Private Ltd., New Delhi, is said to have developed an indigenous thermochemical technology to make this joint and some foreign ribbon manufacturers have also shown interest in purchasing this technology. Lack of proper standards for ribbons is affecting the quality. The Indian Standards Institution has not yet evolved any specifications for computer ribbons and consequently, testing of the ribbons is done by users on a subjective basis. The ribbon industry in India needs support from some government institutions in testing and quality control aspects. As per the import policy of the Government of India, ribbons for electronic typewriters are allowed for stock and sale but the imports for computer ribbons are allowed only for "actual users". Imported ribbons are, however, openly sold. MARK READERS Optical Mark Readers, the computerised scanning systems which read information with the aid of light waves are used extensively abroad but they have not yet found place in India, primarily because computer usage in the country is still not high enough. Further, the equipment could meet with resistance as a number of jobs would be lost and the cost might become high. Accurate data analysis, high speed data scanning, automated data input, reduced paper work, low costs and high flexibility are some of the advantages of OMRs. Unlike in the past, OMRs do not require costly , mini or mainframe computers i as they can be now interfaced with supermicro and microcomputers. Major real life applications of OMR include test and grading applications, attendance and record keeping, payroll preparations, continuing engineering and commercial data tabulation, inventory management and others. The average scanning speed of an OMR is 13 inches per second. NON-STOP SYSTEMS Fault Tolerant Computing, FTC, has become a new branch of computer science which goes by different names like non-stop systems, fail proof computers and zero defect machines. An international workshop on FTC was held in Bangalore recently. Fault avoidance and fault tolerance are two approaches in FTC. In the first approach, a higher reliability is achieved by prior elimination or reduction of causes of failures. This approach does not completely eliminate the possibilities of failures. Even with the most careful system design and fabrication, faults can still occur. The second approach, on the other hand, accepts the inevitability of failures and counteracts the effect of failure through some form of redundancy. Fault tolerant systems are also attractive for unattended facilities where nobody is on hand for repairs or restart. One may think of providing redundancy by hooking up two or more computers but in practice, fault tolerant computer design is more complex. The challenge is to meet these requirements in the face of real-life constraints on synchronous operation of redundant systems, cost, throughput, weight, volume, power consumption and the length design cycle. There is no universal, clear cut solution to the problem of fault tolerance as the decision on the technique to be used, the level at which it is to be adopted and the degree of fault tolerance needed depend on a number of factors like application. price paid and the risk one is willing to take. Aircraft flight control systems, landing systems, rapid transport systems, chemical and continuous process industries, telecommunication, banking and most of the defence applications require FTC. TANDON ON VIRAAT Tandon computers have joined the Indian Navy. They are on board the newly acquired aircraft carrier, INS Vi raat. The 750 feet long aircraft carrier is equipped with seven Tandon computers. Six PCA20s and PCA70 fileserver. networked together by 500 metre cables running between eight decks, connect the flight control, operations, briefing, aircraft maintenance control, management system and store rooms. Networking specialist. Next Computer Ltd., Tandon dealer in the UK. was selected by the Indian Navy to supply and install the system. Running under the Novell software, the network will be used to computerised maintenance management, inventory and stock control, personnel, accounting and undisclosed military procedures. As with most of the military applications, this is a harsh environment for a computer system. It will have to cope with the roll and tilt caused by stormy seas and the vibration of aircraft taking off and landing. SOFTWARE FACTORY Following the example of Texas Instruments, a software factory is being set up in India with a satellite link to the business partner in Italy. Modi Rubber Ltd. and the Olivetti of Italy have signed a collaboration deal. Agreements are also in the offing with Logica of UK and 1 0-20 etektof iixba ocaber 1987 Continental Gummi Werke of West Germany for exports of specialised software. The software unit will be set up at Modinagar in Uttar Pradesh. An earth station will provide direct communication link to Italy and the UK by satellite. The system will also be used for transmission of software packages to customers abroad. The computer systems will be supplied by Olivetti. The unit is expected to begin software export by mid-1988 and the estimated turnover in the next two years is about Rs.10 crores. The Modi group has already joined hands with Xerox for making the copiers. The group recently tied up with Olivetti for a Rs.28 crore project for manufacturing computers. LCA COMPUTERS A separate, high technology corporation may be set up by the government of India to ; manufacture and supply j mission computers needed for Light Combat Aircraft programme, according to Dr. Kota Harinarayana, director of the LCA project. As a part of the efforts to produce components, subsystems and equipment for the LCA within the country, a mission computer research facility will be set up. first to develop the computers and then to manufacture them. This research facility may cost over Rs.60 crores. Not more than one-third of the entire LCA budget would be spent on imports. Out of Rs.1000 crore, earmarked for the LCA development programme, already Rs.150 crores had been spent. For the management of the project. 600 work packages have been evolved to handle different aspects. A high-level Indian defence team has concluded negotiations with j the United States which has agreed in principle to assist 1 India in the LCA project. LASER VIDEO A team of French researchers has developed a new system that helps obtain high resolution images having the I quality of 35 mm ! cinematographic images through a laser video-projector. These images can be directly transmitted for TV broadcasting through satellites, cable networks, or viewed directly on large screens. The images are of 1,200 tines of 2,000 dots for a 16/9 or 5/3 frame site. The image contrast obtained is more than 40 per cent white in a TV it hardly crosses 10 per cent. At present, the images are monochromatic and there is no technical difficulty in 1 having the transmission in colour. The Opto-acousto-eiectronic 1 laboratory of the Universite de Valenciennes and . Hainault-Cambresis. run by Prof. Edouard Bridoux have 1 accomplished this, gaining advantage over several foreign laboratories. This laboratory set up a laser video projector in 1985 using the acousto-op ti cal effect to transfer video information on light beam emitted by a laser. The importance of video images is that shots can be reviewed immediately after filming to verify their quality TV SCENARIO Eighteen years after the introduction of television in India and five years after the colour TV made its entry, the TV market in the country is still struggling to become fully indigenous. The promise of a colour TV for Rs.5000 is yet to be fulfilled. The future market for TV is theoretically very big. Against 1 TV transmission coverage of 70 per cent of the population now. the actual coverage is only 15 per cent. To bring the actual coverage to at least 50 per cent of the population we need another 60 million sets, taking an average of five viewers per set In 1986. approximately 800.000 colour TV sets were manufactured in the country as against 90.000 in 1982. The most important component of a CTV is the picture tube. In January. 1987. JCT Electronics Ltd. in technical collaboration with Hitachi of Japan gave the first colour picture tube made in Incka Subsequently. Uptron and Samtel. joined the CTV tube production in collaboration with Toshiba and Mitsubishi, respectively. The colour picture tube constitutes 30 per cent of the overall cost of a TV set and indigenous production could help in saving foreign exchange. The licenses capacity for CTV tubes is 15 million pieces per annum. JCT proposes to introduce non-glare picture tubes and 14-inch colour tubes. Uptron intends to manufacture colour tubes with 22.5 mm mini neck. Samtel colour picture tubes would be flat square tubes which calls for a substantial change in the production technology and demands additional investment. The picture tubes would also be costlier. The TV industry feels that the government should treat TV as a medium of communication and not a luxury item. As the consumer price of a TV has 50 per cent in the form of levies like excise, sales tax and octroi, the government reduce the ; taxes on TV. NEURAL NETS The main task for scientists I engaged Artificai Intelligence | has been to find out the nature of the symbols and rules which the human mind uses. The conventional assumption has been that once the mind's symbols and rules are known neuroscientists can then figure out how the brain pnysrcally produced them. Those who build neural networks now are challenging this assumption. John Hopfield and his colleagues at California Institute of Technology have been building a computing machine that operates on an entirely different principle than the conventional, step by step symbol processing. The new machine would be modelled after the brain, a vast network of neuron-like units that operate on data all at once. Scientists have succeeded in simulating such "neural nets" on powerful conventional computers. It represents a radical shift in designing computers that think and possibly, it may change our thoughts about the process of thinking. NETalk is one machine that can learn through algorithms and this 200-unit neural net has learned to read aloud. Neural nets are still in the expen mental stage and many cognitive scientists are sceptical about their potential. I Yet many others feel that neural nets will enhance our understanding of how the brain works and help us build better Al systems. 1967 10-21 SINGLE-CHIP MICROCONTROLLERS Single-chip microcontrollers, such as Intel’s MCS-51 series described in this article, are currently finding their way in more and more industrial control systems. They otter a remarkably low chip-count as well as ease of programming when the computer is assigned a single task. MCS-51 Microcontrollers. Technical features: • 8-bit CPU optimized for control applications • Extensive Boolean processing (single-bit logic). e 32 bidirectional and individually addressable I/O lines, e 128 or 266 bytes of on-chip data RAM. • 2 or 3 16-bit timer/counters. e Programmable, full duplex UART. e 5 or 6 source interrupt structure with 2 priority levels. • On-chip dock oscillator • 4 or 8 Kbytes of on chip program memory (8751 & 8752: EPROM), e 64 Kbyte program memory address space. e 64 Kbyte data memory address space. • 111 instructions (64 single^ cycle). e Decimal and hexadecimal operations, e 8 Kbyte BASIC interpreter I8052AH BASIC). e Built-in EPROM programmer under BASIC control (8052AH-BASIC). e Special BASIC commands for I/O, counters, and serial interface ' (8052AH BASIC). For many applications, the use of a dedicated microcontroller has obvious advantages over a standard microprocessor like the 6502 or Z80. This is mainly due to the microcontroller be- ing tailored to perform only the necessary functions. Input/out- put lines, for instance, are available direct on the chip, ob- viating the need for a complex set-up with individual I/O chips, interfaces, buffers, and all the necessary hardware for address and data decoding. Often, the microcontroller holds a programmable timer/ counter also, and has an exten- sive instruction set for bit manipulation. The Types 8051 and 8052 are single-chip microcontrollers from Intel’s extensive MCS-51 series. Over the past years, they have found an increasing num- ber of applications in industrial processing systems. This intro- duction aims at familiarizing you with the 8051, 8052 and 8052AH-BASIC, which are ver- satile and powerful controllers that enable designing and building compact, micropro- cessor-based, equipment for a wide range of applications. The MCS-51 family Intel’s MCS-51 family of single- chip microcontrollers consists of the devices listed in Table 1. It should be noted that the type indication 8051 often refers to the the MCS-51 family as a whole The pinning and func- tional representation of some of the chips in the MCS-51 family appear in Fig. 1 and Fig. 2 re- spectively. The 8051 is a con- troller with 4 Kbytes of on-chip mask programmable ROM. The Type 8052AH, a HMOS II chip is an an enhanced, downward compatible version of the 8051. It is important to note that the 8051, 8051AH and 8052AH are mask-programmable devices. This means they are only available in large quantities since the on-chip program memory can only be loaded by the manufacturer. The 8031, however, differs from the 8051 in not having the on-chip ROM Instead, it fetches all instruc- tions from external memory, and is, therefore, ideal for writing and testing software for the 8051. Similarly, the 8031AH and 8032AH are the ROM-less versions of the 8051AH and 8052AH, respectively, while the corresponding EPROM ver- sions are identified as Types 8751 and 8752. Software security can be provided by making the EPROM contents inaccessible for external read devices. A separate product, the 8052AH- BASIC, is essentially a 8052AH with a powerful and fast BASIC interpreter programmed in the on-chip ROM. This microcon- troller chip is particularly in- teresting for one-off appli- cations, and will be reverted to in greater detail. Memory organization Essentials of the memory struc- ture of chips in the MCS-51 series appear in Fig. 3. In brief, the memory is divided in 2 blocks of 64 Kbytes. One block is the program memory, the other the data memory. The .lower 4 or 8 Kbytes of the 1 c n aiac i tki m c > P11C 3 PUT 4 P1IC5 PlJCl P14C 7 pi rc a *rr c • RIO PM C It nopjic ii iff Pll c 13 STi m C 13 it n* c 14 ti am c is m* pm r it mm c ip ITALIC it ITAL1 C It WSt » h tree ptst AOS At 1 AOi Rt-2 AOJ $ 3 At S AOS 3 Att AOS J At 7 AO 7 JlhtAVOO K^AltWC 3 TStt 3 A3 7 A1S 17f] A3SA14 3 A3-S At 3 39|~1 A34A13 Mp A3 J All MC3 A3 3 Alt 33C3 A3.1 At lip AM At 87074-1 ' Fig. 1 Pin assignment for the chips in the MCS 51 series. 10"22 etektor inda October 1987 Fig. 2 Showing the port line functions when the controller operates with external memory. Table 1 ttovlc* infcem*l Memory Umar*, Event Counion Interrupt* Program Dale 8052AH 8K x 0 ROM 256 * 8 RAM 3 x 16-Bit 6 8051 AH 4K x 8 ROM 128 x 8 RAM 2 x 16-Brt 5 8051 4K x 8 ROM 128 * 8 RAM 2 x 16-Bit 5 8032AH none 256 x 8 RAM 3 x 16- Bit 6 8031 AH none 128 x 8 RAM 2 x 16- Bit 5 0031 none 128 x 8 RAM 2 x 16 -Bd 5 8751 H 4K x 8 EPROM 128 x 8 RAM 2 x 16- Bit 5 8751 H- 12 4K x 8 EPROM 128 x 8 RAM 2 x 16-Bit 5 Table 1 The MCS-51 family of microcontrollers. 3 64 K EXTERNAL 64 K 4095 overlapped ipace INTERNAL 255 255 128 SPECIAL FUNCTION REGISTERS INTERNAL 128 INTERNAL OATA RAM program counter uirs 34 program memory internal data memory extern* data memory Fig. 3 The MCS-51 memory structure. 4 Fig. 4 The MCS-51 architecture. program memory is on-chip ROM. In the ROM-less con- trollers, all program memory is external, and may, therefore, be RAM or (EP)ROM. The micro- controllers can only read from the program memory, which holds the sequence of ex- ecutable processor instructions in the form of machine code. The data memory is used for storing variables, intermediate results of calculations, pro- cessed datawords, look-up tables, and the like. Up to 64 Kbytes of external ROM, RAM or EPROM can be ad- dressed in the external data memory space. A number of special register functions are located in a separate 128 or 2S6 Byte RAM area. The main registers are the accumulator, register B (for multiplication and division), status register, stack pointer, data pointer (2x8 bits or 1x16 bits), port 0. . .3, the double serial trans- mit/receive register, the 16-bit timer/counter registers, capture registers for the third counter (8052), and the command regis- ters for special functions (inter- rupts, RTC, serial I/O). Most MCS-51 instructions are executed in a single machine cycle, he., within 12 clock periods. When the clock fre- quency is 12 MHz, one machine cycle lasts 1 js, so that the pro- cessing speed of the MCS-51 chip equals that of a 6502 CPU running at 2 MHz, or a Z80 at 8 MHz. A noteworthy aspect of the microcontrollers is then ability to manipulate fewer than 8 bits at a time, relieving the programmer of cumbersome bit-masking routines. Buses and ports The basic internal structure of a controller in the MCS-51 family is shown in Fig. 4. It is seen that there are, in theory, 4 bidirec- tional, 8-bit wide ports. In prac- tice, these are only available when the internal memory (ROM or RAM) is used. In all other cases, ports 0 and 2 func- tion as the data and address bus (refer back to Fig. 2), so that 2 ports remain for I/O appli- cations. Port P2 supplies ad- dress signals A15 . . . A8, port PO address signals A7...A0 and databits D7...D0, multiplexed with the aid of the ALE pulse (adress latch enable). Outputs RD and WR are simply output lines on port 3, internally pro- etafcto t indiodobM 1967 1 0“23 giammed for supplying the pulses for read and mi l e oper- ations in die external dan memory The read strobe for ex- ternal program memory is the signal PSEN (program store enable). It is interesting to note that PSEN . as well as ALE. is ac- tivated twice m every machine cycle during execution of a program in (EP)ROM, because two bytes are fetched suc- cessively during each cycle PSEN remains inactive when the machine code is stored m the interna! memory, and the external memory (if available) is empty. PSEN is not normally used in designs incorporating the S062AH-BASIC because the internal ROM holds the BASIC interpreter Input EX (external address) ss activated when the processor is to read opcodes from the external memory, rather than from its internal (EPJROM. The EA input is also used for applying the 21 V pro- gramming voltage for the inter- nal EPROM (8751. 87521 Timers and counters It was already seen m Table 1 that the 8062 has one more 16-bit tuner /counter than the 8061. Below is a necessarily concise overview of the func- tions performed by the timer/ counter blocks. In the tuner mode the register contents are incremented once in every machine cycle The maximum count rate is there- fore ‘'nth of the processor clock speed. In the counter mode the register contents are incremented on the trailing edge of the signal applied to in- put TO. TL or T2 (the latter is only available on the 8052). The maximum count rale is ‘'trth of the processor clock speed. Counter/timers 0 and 1 have 4 programmable modes, includ- ing 8 or 16 bit operation, and automatic loading of a preset value Timer/counter 1 can be | programmed to function as a baudrate generator for the asyn- chronous serial interface Timer/counter 2 (8052 only) has 3 modes; 16-bit automatically reloadable counter, 16-bit cap- | ture counter, and baudrate gen- erator. The serial port All microcontrollers in the MCS-51 family feature an on- chip bidirectional serial inter- Tabte 2 MIIHHEIX OrtlttlOVN ADO A.R« ADD A. dwelt ADD A. *Ri ADD A Aim ADIX A Rn ADIX A.darect ADIX A..*’Ri ADIX AAdata SI BB A Ro SI BB A direct SI BB A R i SI BB \.*da«a INC A INC Rn INC direct INC £R; DEC A DEC Hr DEC direct DEC $Re INC DPTR Ml 1 AB DIV AB DA A LOCK AL OPER All Mrwnvtir we AM A.Rn ANI A direct AN| A.C*R» ANI A.«data ANI direa.A ANL direct. *dau ORI ARir OR I A.direct ORI A.M* ORI \ Atifa ORI direct „A ORI direct Udu u \R! A.R» \R1 Ajdwert \R! A a Rt XRL Ahbu XRI direct. A XRl duect.*data CLR A CPI A R! A RLC A RR A RRt A SWAP A DATA TRANSFER Mmomhk MOV A Re MOV Adnta MOV A.:«R» MOV A.«daea MOV A MOV Rtr. direct MO\ Rn.Nljta MOV direct. A MOV direct. Rn MOV direr: .direct MOV direct * R MOV direct. •data MOV •a'Ri.A MOV ^ Rut: rev c MOV iRi*dau MOV DPIR.bdau c jc Add dwrct Me to Accw Add indirect R AM la 4 Add immediate drf Add trtwer to Axuoubtoi with Cam Add direct Ktt to A with Cam fbg Add indirect R AM Bo A with Carrs flag Add uuf ct e d va fle data to A with Cain flag Subtract register Crony A with Borrow Subtract direct htr from A with Borrow Subtract iidirct RAM from A w Borrow Subtract rnxaned data from A w Borrow Increment register Increment direct byte hermrst indirect RAM Decrement repsttr Decrement direct bvie Otamna twstoevt R AM facTcmrtsc Ibu Pataae* Muftspiy A A B DMk A h*. B fteifflia! Adtua* Accwmtdatc^ Mott repiKT bo Accw Move direct byte to J Move larfmsc* RAM t*a 4 Move immediate data to Atcarrmbigr Move Accuawdbeor to icftttr Move direct byte m register Move mmedwBe data to register Move Acc iumd aiof to duett bv*e Move register to dirre: byte Move direct byte ro direct Move ndirect R AM t» direct by«r Move iisordsut data to d ir ect byte Move Accwniabtar to indirect RAM Move direct byte to indirect RAM Move ixr.medwfc data to mdtren RAM I odd Data Pc-r.rer with a Ib-btt coasts n AM) ftpuer bo .Auamdiior AND dir ect bvte to Acciusu*6«oe AND indirect RAM to Accwmufcaiof AND oacncduic data ro Accumatato AND AaanawiatOT labnxi byte AND UBmediatir data to direct bvte OR tqpsicr :o Acnmublor OR direct byte to OR nafmet RAM to Acci OR OR Aecumttfcuoe to direct byte OR immediate data to direct byte EscftrMvc-OR register to Accumwlttfcr F uiwwrOR direct byte so Accsmuiaio' F idiauvr-tHI ladrrrt R AM «o A fc uiiivvr OR MMKrimac data to A EvhweOR Accumwfcaroc to direct byte F. uitrmtOR i mmed iate data to direct Clear Accumulator Complement AecwmoJaeor Rotate Acundaior left Rotate A Left through the Cam flag Rotate Accurawiaror Right Rotate A Right tfuoogh Carry flag Swap ntbbfcv wither the Adiuretuiur.'r Bnr < I Cyc I DATA TRANSFER (cwwt.l MOVC A.#A+DPTR MOVC V£A*PC MOV X A.#Ri MOVX A.»DPIR MOVX SRLA MOVX SrDPTRjA PUSH POP XCH A.Rn XCH A .direct XCH A.«Ri XCHD A«Ri Move Code byte rdatire to DPT R to A Move ('ode byte relative to PC to A Move external RAM (Tbit addrl to A Move Ettcmal RAM tlb-tnt addr) to A Move A to External RAM (fMwt addrl Move A to External RAM (16-bil addrl Push direct bvtc onto stack Pop d i reel byte from vtack t vc ha ripe register with Accumulator F&changr direct byte with Accumulator Exchange indirect RAM wtth A F vrhangr tow-order Digit tnd RAM » A Byte C,c I 2 boolean variable manipi lation Clear C am flag Clear direct bu Set Cam flag Set direct Bit Comp kmtn i Carry Hag Corepkrerai direct bit AND direct bit to Cany flag AND complement of direct bts to Carry OR direct bit to Carry flag OR complement of direct hit to Carry Move direct brt to Cam flag Move Cam flag h> direct bit PR 04. RAM AND MACHINE CONTROL AC AM LCAI I RE I RET! VJMP LIMP SJMP IMP JZ JNZ JC JNC JB JNB JBC CINE CJNE CJXE CINE DINZ DJNZ NOP addrl f addr lh addrl! addr Sf' rel $ A- DPTR ret ret ret ret bit .ret bn. ret brt. ret A direct .ref A •dau.ret Ro.*dau.ret y-Ri. ( daa.rci Rn.ret direct, ret Byte Cyc Description Absolute Subroutine Call t.ocg Subroutine (all Return from subroutine Return Irotn interrupt Abiotutc Jump Long Jump Short Jump (relative addrl lump indirect relative to the DPTR lump if Accumulator tv Zero Jump if Accumufcuor is Not Zero Jump d Carry flag is vet Jump if No Carry flag Jump it direct Bit *ct Jump rt di reci Bit Not vet lump if dtrect Bit a vet A Clear bit Compare direct to A A Jump it Not Equal Comp i mined to A A Jump it Not Equal ( omp '.mined «o rcg. A Jump d Not Equal Comp emmed to ind A Jump if Not Equal tfecrrmrni register A Jump if Not Zero Decrement direct A Jump if Not Zero No operation Byte Cyc Rn direct •R> *dacu Niaulh bu Notes on whirl* Working register R0 R7 1 23* internal RAM locations. any I O port, conttol or status register Indirect internal RAM location addressed bv register R0 or R t *-bu constant included its instruction 16-btt constant mcfwded as bytes 2 A 3 of instruction IS software flags, any I O pin. control or statin bit iXrsuaaturn address for l CALL A I JMP may be anywhere within the M- Kilobyte program memory address space Destination address for ACAI l A AJMP wiD be within The same 2- Kilobyte page a* program memory as the first bite of the following SJMP and al! conditional tumps include an !*-bu offsei byte Range is *12? - 12* bytes relative to fir 4 byte of the following instruction npynghted © Intel Corporation I9N Table 2 The complete instruction set of the 8051 8062 series of microcontrollers from Intel. face (UART) capable of trans- mitting and receiving data sim- ultaneously. A special data buffer is provided for the asyn- chronous receiver to speed up communication with serial per- ipherals. The serial port can be pro- grammed to operate in 1 of 4 modes, with software-con- trolled baudrate and data for- mat. All the usual baudrates up to 19,200 can be selected, as well as clock rates up to 1 MHz for use in networks and multi- processor communication sys- tems. The clock speed selec- tion is effected with the aid of the timer/counters. Interrupts and the instruction set The 8051 and 8052 recognize 5 and 6 int errupt so urces , re- spectively: INTO and INTI (pro- grammable for pulse level or pulse edge detection), timer/ counters 0 and 1 (and 2 on the 8052), and the serial port. Inter- rupt programming with 2 pri- ority levels is completely inde- pendent of the hardware con- figuration. Each of the 5 or 6 interrupt sources can be as- signed an individual vector (ad- dress pointer). Thus, when an interrupt request is received, the processor jumps to the rel- evant service routine after having saved the contents of the program counter onto the stack. The full instruction set of the controllers in the MCS-51 family is shown in Table 2. The 8052AH-BASIC The Type 8052AH-BASIC micro- controller is undoubtedly the most interesting of the MCS-51 family, since it offers an elegant and efficient way of writing con- trol programs for computer- based projects. Intel have loaded the 8 Kbyte ROM in this chip with a powerful BASIC in- terpreter, while an additional counter/timer. T3, enables split baudrate operation of the serial interface. The BASIC instruction set (version 1.1) is listed in Table 3. On close examination, it is seen that special commands are included for functions otherwise requiring assembly language. After numerous tests and evaluations, it was con- cluded that the 8052AH-BASIC is eminently suitable for various applications connected with remote data logging, instru- i mentation and measurement, and industrial process control. The BASIC interpreter is, of course, slow as compared with machine language routines, but has the advantage of being programmable in "normal” language. Also, debugging and editing programs are signifi- cantly less difficult, and inex- perienced programmers can learn about the processor’s capabilities fairly quickly with a minimum of hardware. It is reassuring to know that Intel can supply a 200-page refer- ence manual for 8052AH-BASIC programmers. Some special features of the 8052AH-BASIC deserve par- ticular attention. The controller can program virtually any type of EPROM if the correct pro- gramming voltage is applied to pin EA. Both the "old" (50 ms per address) programming standard and several versions of the interactive algorithm are supported— see the last 14 items under Commands in Table 3. ram, rom and xfer are commands for manipulating and transferring blocks of memory. The versatily and programming power of the BASIC processor is evident from a number of special Statements baud sets the data transfer rate on the previously mentioned ad- ditional serial channel, call enables calling machine language subroutines from BASIC, clocki and clocko con- trol a real-time clock, and clears initializes the data stack, which is primarily used for ex- changing machine language parameters, or for storing local variables. Further interesting possibilities are offered by ontime, a statement that allows generating an interrupt at a pre- programmed time, onexi, for jumping to a subroutine follow- ing an INTI interrupt request (interesting because external and timer interrupts can be dealt via BASIC), pho and phi for printing in hexadecimal format, push and pop for stack manipulation in BASIC, and, fi- nally, pwm for generating a pulse-width modulated signal. The statements also include a number of useful instructions for calling up interpreter routines direct from BASIC: uu, uio, uoi and uoo. The third column in Table 3, Operators, not only lists the well-known arithmetic and logic operations, but also a number of special function operators, starting with cbyi >. These operators offer direct control over I/O lines and memory locations, cbyi > and dbyi ), for instance, give read /write access to the inter- nal program and data memory, respectively, get allows a character to be read from the serial interface. The remaining special operators, up to and in- cluding timerz, are intended for reading from and writing to the register indicated by the rel- evant abbreviation. Operator xtal provides the pro- cessor with information about the clock frequency used. This is needed to ensure correct op- eration of the real-time clock. The status of the memory can be read at all times thanks to operators mtop, which returns the highest available memory location, len, for information on the length of the program, and free for the number of available memory locations. Quite remarkably, the 8052AH-BASIC allows BASIC functions to be called up from assembly language. These functions in- clude floating point calcu- lations, complex arithmetic operations, and input-output routines. The microcontrollers in the MCS-51 series will be at the heart of a number of projects currently under development in the Elektor Electronics design department. Details on avail- ability and programming will be announced in due course. Th;DM Source: Embedded Controller Handbook. Intel Corporation. MCS-51 is a registered trade- mark of Intel Corporation. Intel Corporation (UK) Limited • Piper's Way • Swindon • Wiltshire SN3 1RJ. Telephone: (0793) 696000. Telex: 444447 INT SWIN. For distributors in the UK see Infocard 512 in this issue. •laklor irxha October 1987 10-25 COMMANDS STATEMENTS OPERATORS RUN BAUD ADD ( + ) CONT CALL DIVIDE O LIST CLEAR EXPONENTIATION (**) LIST# CLEAR(SAI) MULTIPLY (*) LISTfa CLOCK(1 &0l SUBTRACT ( - ) NEW DATA LOGICAL AND f AND ) NULL READ LOGICAL OR i, OR.) RAM RESTORE LOGICAL X-OR ( XOR ) ROM DIM LOGICAL NOT XFER DO- WHILE ABS( ) PROG DO-UNTIL INTO PROG1 END SGN{ } PROG2 FOR-TOSTEP SQR( } PROG3 NEXT RND PROG4 GOSUB LOGO PROG5 RETURN EXP< ) PROG6 GOTO SINK FPROG ON-GOTO COSO FPROG 1 ON-GOSUB TAMO FPROG2 IF-THEN-ELSE ATN{ ) FPROG3 INPUT FPROG4 LET ASCI) FPROG5 ONERR CHR() FPROG6 ONEXi CBY( ) ONTIME DBY() PRINT XBY() PRINT# GET PRINTS IE PHO IP PHO # PORTl PHO (n PC ON PHI RCAP2 PHI # T2CON PHI (a TCON PGM TMOD PUSH TIME POP TIMERO PWM TIMER1 REM TIMER2 RETl XTAL STOP MTOP STRING LEN UIO&O) FREE UOO 40) LDin ST(n PI IDLE RROM 87074-5 Table 3 The BASIC instruction set of the Type 8052AH-BASIC includes a number of powerful and efficient commands, statements, and operators. TESTING THE INSTRUMENTS OF TOMORROW by Adrian Morant The increasing use of digital technology, rather than the previous generation of ana- logue systems, in both satellite and terrestrial communications, has resulted in a demand for widely differing testing tech- niques. Even though the inte- grated services digital network (ISDN) may largely still be in' the future, planning for the necess- ary testing must be carried out in parallel with the planning of the networks themselves. These needs have been exacer- bated by the introduction of fibre optics which allows a single fibre, with its diameter measured in micrometres rather than millimetres, to carry far more traffic than a bunch of coaxial cables, each 10 mm in diameter. In addition, there have been major technical advances in mobile communications. Here, one of the outcomes is cellular radio, which relies for its oper- ation on sophisticated tech- niques originally developed for radio equipment for military and defence purposes. Reliability essential Whereas previously there were separate networks for voice, telex, data and so on, the trend is towards the one ISDN. The fully digital transmission and switching, plus the integration of a wide range of services on to the one digital network, in- crease the need for great re- liability in the networks. The requirements become even more stringent since, with the increasing use of computer- to-computer communications, users are demanding a larger degree of network availability. Nowhere is this more apparent than in the City of London, where the financial community has moved with the deregula- tion known as the "Big Bang", to electronic trading. With in- dividual deals worth £1 million or more— and the value of an entire day's trading running into 10-26 •l«ktor india October 1 987 thousands of millions— loss of telecommunications is not so much a problem as a disaster. In these circumstances, testing must be carried out wherever possible, both as a form of preventive maintenance, and in the event of failure. In the latter case, it is frequently cost effec- tive to use what may, at first sight, be excessively sophisti- cated equipment, because it will provide quicker and better results. Wide range of users Marconi Instruments Ltd, one of the traditional names in test equipment, recently an- nounced its data communi- cations analyser model 2871 for detailed error performance testing. It consists of a pattern generator and error detector, plus a powerful processing fa- cility, providing an extensive range of measurement options. The menu driven instrument, which uses a cathode ray tube (CRT) display, provides for both out-of-service and non-intrusive in-service monitoring and testing at up to 150 kbit/s data rates. It is aimed at three main user groups: digital network support staff involved in maintenance, installation or commissioning activities', telecommunications design and development engin- eers; and production testing and quality assurance (QA) departments. These users oper- ate in public and private com- munications carriers, energy utilities, military and govern- ment networks. They include also telecommunications equip- ment suppliers. Continuous monitoring Among the special features ot the 2871 is the ability to present test results, not only as bit error ratios, but also as detailed infor- mation about the type and time of the error occurrence. This is essential when diagnosing fault conditions in telecommuni- cations networks. In addition, it is designed to carry out 24 hour unattended error performance monitoring. This is of increasing importance for today's users, whose net- works operate around the clock but who find difficulty in recruiting the technical staff to maintain them. Where the distances spanned by telecommunication cables, either going point-to-point or linking switching centres, are more than just a few kilometres, it is necessary to insert elec- tronic equipment to compen- sate for losses in the cable. With coaxial cables this is typically every five or 10 km. Today’s single mode fibre optic cables allow paths of up to 40 km or even more without regener- ators, so that when faults in the cable do occur, it is necessary to locate them with some accu- racy. A precise method The technique used, based on The Marconi 2871 data communications analyser. radai, is known as time domain reflectometry (TDR) It relies on the fact that a portion of a signal pulse sent down the cable- electrical in the case of coaxial cables and consisting of light with fibre optics— is reflected back towards the source when it encounters a discontinuity. This could be an actual cable fault, such as a break in the cable, or a point where there is a slight kink. While it might not be a problem at the time, it could indicate potential trouble for the future. Knowing the velocity of propa- gation, that is, the speed of the signal down the cable, the in- strument can be calibrated | directly in distance of the fault from the sending end where the instrument is sited. The CRT display, together with cali- brated digital controls, allows the operator to learn both the location and type of the discon- tinuity. Cossor Electronics Ltd had been manufacturing cable TDRs for a number of years before it introduced units for fibre optical applications. In ad- dition to models for the 850 nm wavelength at which the earlier optical systems operated, the company's range now includes the model OTDR 213S, which has been specifically designed to handle single mode fibres at 1300 nm up to distances of 40 km. Higher frequencies In addition, the company is launching a new instrument, the OFL 215, designed to operate at the 1550 nm wavelength, which is increasingly being adopted for telecommunications net- works because of the lower at- tenuation window it offers. The trend in mobile radio systems is to move to ever higher radio frequencies. Famell Instruments Ltd has pro- duced a communications test set, model CTS520, designed for service and production testing of simplex or duplex radio transceivers, paging equipment and base or relay stations in frequency bands up to 520 MHz. It provides the measurement capability of nine separate in- struments, plus weighting filters and radio frequency (RF) power load, housed in a readily transportable case. They can be used either independently or together to carry out a com- prehensive variety of tests. The instruments include syn- thesized RF signal generator, RF counter, modulation meter, RF and audio frequency (AF) power meters, AF voltmeter, distortion analyser, signal inter- ference noise and distortion (SINAD) meter, and a selective calling (CTCSS) tone generator. Many tests Only four connections are necessary to the device under test, and measurement are displayed on either light emit- ; ting diode or analogue meters. An internal loudspeaker is fit- ted. With the test set, it is possible to carry out a wide range of tests that normally require a host of separate instruments. Because of the complexity involved, these frequently need to be car- ried out by more highly skilled technicians. Famell also manufactures test gear covenng the frequency bands extending to 1 GHz employed by modem cellular radio networks, such as those operating in Britain. Racal-Dana Instruments Ltd is another important company on the scene. It is part of the Racal Electronics Group, well known throughout the world for tac- tical radio equipment, some of which employs frequency hop- ping. Here, the radios change from one channel to another many times a second in a previously agreed pseudo- random sequence to avoid be- ing jammed and, at the same time, to give a degree of com- munications security. Quick response In the same way, when a cellular phone is moved from one cell to an adjoining one, it has to switch on to a channel as- sociated with its new cell. This has to be carried out in a speci- fied and very short period of time. Consequently, test gear used in conjunction with cellu- lar systems must respond quickly enough to meet these requirements. The Racal-Dana 9087 signal generator, for example, is capable of implementing over 1,000 complete changes of fre- quency per second in its fast learn mode. It is a complete in- strument, offering excellent purity, a wide range of internal and external modulation facili- ties, and many output ampli- tudes. It is an extremely versatile in- strument for use in most areas involving frequency agility. Modem advanced instrumen- tation often involves automatic testing, so the general purpose interface bus (GPIB) compati- bility allows the 9087 to be con- nected into a complete auto- matic test equipment (ATE) system. Similarly, the now well estab- lished model 1998 frequency counter is a microprocessor based instrument which measures frequency, time inter- vals and so on over the fre- quency range to 1.3 GHz and is consequently an ideal instru- ment for testing modern com- munications systems, including cellular radio and satellite systems. Again, being GPIB compatible, it is suitable for ATE applications. EW PRODUCTS • NEW PRODUCTS • NEVj High-stability subminiature crystals Manufactured by Japanese crystal specialist Citizen Watch Crystal Company using the AT- cut cleavage technique, the operating frequency of Quantelec’s new CSA quartz os- cillator crystals drift less than ±30 ppm over 70 ° temperature range. The new crystals, designated the CSA 309 and CSA 310, are available in frequencies from 3.5 to 3.9 MHz and 4 to 20 MHz | respectively. All are designed i for operation between —10 and ■ +60 °C with negligible fre- i quency drift between + 15 and I +40 °C. CSA crystals are housed in a i subminiature hermetic pack- age, 9 mm long and 3 mm in diameter, which imparts ex- cellent shock and humidity re- sistance. They will survive a 75 cm drop on to a hard surface without degrading the elec- trical performance or affecting the sealing. Two load capacitances are listed, 16 pF or 30 pF, with a choice of 50 or 500 microwatts j ; optimum drive level. The shunt I capacitance is less than 5 pF. Quantelec Limited 46 Market Square Witney Oxen OX8 6AL. Telephone: (0993) 76488 Telex: 837851 SELECT G. (3654:18:F) I elefcloi indis October 1967 10-27 STREAM ENCRYPTION by B.P. McArdle One of the evils peculiar to the computerized world is hacking— the unlawful accessing of computers. One way of effectively combatting this nefarious activity is encrypting the data. Encryption is the process that turns data into secret form. The original data is known as the plaintext or cleartext and the encrypted data as the cipher- text. If the plaintext is P and the ciphertext is C, the encryption operation is described by A l P]=C [1] where if is a parameter called the key which is used to vary E. The effect of a change of key is to generate a different C for the same P. The user chooses a par- ticular key from a set of poss- ible keys (K) and encrypts the plaintext. The ciphertext is stored or transmitted over a channel as illustrated in Fig. I to a receiver. The receiving oper- ator must know the particular key in use to enable him to recover the plaintext with the inverse or decryption operation £k’(Q=75k (C)=P [2] Exhaustive Search and is based on the fact that only the true key will produce meaningful text; (b) deduction of the true key from known plaintext-cipher- text pairs should be imposs- ible except by an exhaus- tive search— this is called a Known Plaintext Analysis. Linear functions A function / is said to be linear if it satisfies the following two conditions (1) f(x+y)=m+f(y) (2) f(ax)=af(x) where a is a constant. If these conditions are not met, the function is non-linear. It has been stated that linearity is the From the point of view of main- taining secrecy, it must be as- sumed that a cryptanalyst (hacker) would have unlimited ciphertext and would probably know the method of encryption (which means £), but would not know the particular K. To en- sure real secrecy, two main tests to assess cryptosystems have evolved over the years: (a) the set of possible keys must be large enough to make a search with each key in turn impractical. This is called an 10 28 elektor india October 1 987 friend of the cryptanalyst and the enemy of cryptographers. This statement will become clear later in the article. Euler's Totient Function Euler's Totient Function states that (fl) is the number of in- tegers less than n that are rela- tively prime to n, that is, have no common factors. For example, 0(31)= 30. Stream encryption In electronic terms, the plaintext is a binary sequence that consists of Is and Os. The encryption operation is a Boolean Exclusive— Or Logic Operation, illustrated in Fig. 2 where a bit of the plaintext Pi and a key bit Kj are combined in an exclusive-or gate to gener- ate Ci. The operation is de- scribed mathematically by C,HP,+K,) mod 2 [3] The reasons for using this oper- ation as opposed to OR or AND are that C is 0 or 1 with equal frequency and that the decryp- tion operation only requires the same operation: PMQ+Ki) mod 2 [4] The following example for encrypting/decrypting five bits explains the overall procedure Encryption operation Pi : 1 0 1 0 1 Kj : 0 1 1 0 0 Pi+K : 1 1 2 0 1 (Pi+K) mod 2 : 1 1 0 0 1 Decryption operation Ci ; 1 1 0 0 1 K, : 0 1 1 0 0 Ci+K, : 1 2 1 0 1 (Cj+K,) mod 2 : 1 0 1 0 1 To summarize, a stream crypto- system is essentially a deter- ministic process for generating a key sequence (AT/) which should have approximately equal numbers of Is and Os, and have a very long period so as to appear random to an observer. Linear-feedback shift registers A linear-feedback shift register is illustrated in Fig. 3. Each stage is a JK bistable (flip-flop). The output is taken from the last stage. The feedback function generates successive states from an initial state or seed as follows: K — f{Kj - 1 ,K;—2 , . . . ,Ki i) for ]>r [5) which for a linear-feedback ar- rangement may be rewritten as K=1 ( LK ,-\ ) mod 2 for j>r [6) /= 1 Ai=l for latch i closed [7] £i=Q for latch 1 open [8] To ensure that (Kj) has an ap- proximately equal number of Is and Os, latch r is usually left closed. If, for example, r=5 with Li open and the other latches closed, the linearity of / can be shown by the following results: /(1,0, 1,0,1) =0 |9) /(1,1,1,1,0)=1 [10] /[0,1,0,1,1)=1 [11] The 3rd state on the left can be generated from a modulo 2 ad- dition or an exclusive-OR be- tween the other 2 states. The same result can be obtained on the right-hand side. Thus, the arrangement satisfies the first condition for a linear function. There is no need to consider the second condition, since a is 0 or 1 in modulo 2 arithmetic. Note, however, that the state "all Os” always generates itself. In the operation of the shift register, each state has a unique predecessor and successor. The total number of possible states for r stages is 2', but the state "all Os” is never used, which means that the maximum possible period is 2'— 1. In the previous example, the key se- quence from a seed (1,0,1, 0,1) is (1,0, 1,0, 1,0, 0,1, 0,0, 0,1, 0,1, 1,1, 1,1, 0,1, 1,0, 0,1, 1,1, 0,0, 0,0,1) and has a period 31, which means that the choice of latches results in maximum period. Obviously, not every arrangement of the latches produces maximum period. There are is Euler’s Totient Function. For r=5, this gives *3+Ki + 1+Kj) mod 2 [26] For the seed (1,0, 1,0,1), the key sequence is (1,0, 1,0, 1,0, 1,0, 0,0, 1,1, 1,0, 1,0, 0,1, 0,1, 1,0, 0,1, 0,0, 1,0, 0,1,1) and has period 31. The secrecy depends on the cryptanalyst not being able to deduce Kj to mod 2 [18] 'loioHioio-iiioi-iiiio-iini-oiiii-ioiii-oioiiJ elefcior india October 1967 10*29 Ki • 4 from K'i to K'j*A (assuming a worst case analysis where both functions are known). In this simple example, such a deduction is turgid rather than impossible. But an actual com- mercial system would have r=128 or r=256. In designing such a system, the feedback logic would be one of d><2 r — l)/r latch arrangements that pro- duce a maximum period of 2 r — 1. The non-linear logic could be chosen with a variety of methods, but the following is simple and straightforward. In Fig. 6, the output or inverted output of each stage (bistable) is connected to an AND gate with the constraints: (a) each gate has only 2 inputs; (b) the span of the inputs does not exceed the number of stages. For example, the pairs 1-4, 2-6, 3-8, and 5-7 satisfy these con- ditions. The resulting function is not necessarily non-linear in the strict mathematical sense, but for a large value of r, it would be quite complex. A cryptanalyst would have to discover a method of solving equations which have non- linear operations or use an exhaustive search. For r=256, this would be impractical. Therefore, this arrangement is reasonably secure. A useful hint for designers is to include a fa- cility to vary the logic ar- rangements such that the same functions are not used too often. Congruence generators The congruence generator method is essentially a com- puter algorithm for generating a sequence of numbers from a seed Xo as follows: number sequence X;=(AX+B) mod M binary sequence K : =X, mod Af Thus, K is 0 or 1, depending on whether X is even or odd. The modulus, M, is the largest prime that can be fitted to the processor’s word size, while A and B are integral powers of some prime factor. The gen- erated sequences are periodic, because once the seed is re- produced, the complete suc- cession of results after the seed also repeats. For example, .Xo=8191 A = 13,077; 5= -6925: M= 32,767 has period 1050. But the simplicity of the operation is also its weakness. Generally, A, B, and M are machine con- straints, which means that X o is the only parameter that is varied. In addition, some seeds have short periods which in turn limits the choice of seed. In applying test 2, it must be as- sumed that a cryptanalyst would have all the details except the seed. Thus, the secrecy depends on the diffi- culty of deducing Xi from K>. For instance, if Kj=\, for a 16-bit word, Xi is an uneven number between 1 and 2' 6 — 1. An exam- ination which would try each possible number in tum in Eq. [26) would not be impractical. Consequently, this system im- plemented on the standard desk-top would not satisfy test 2 . X 2 mod PQ generator In this method, a sequence of numbers (Xi) is generated from a seed Xa as follows: number sequence Xi=Xj - 1 mod N binary sequence Ki=Ki - 1 mod 2 The modulus, N, is the product of two large primes P and Q that are congruent to 3 mod 4 and gcd(Xa,N) = \. Therefore, Ki is 0 or 1 depending on whether X, is even or odd. The set of poss- ible seeds has is Euler’s Totient Function. The main diffi- culty here is implementation on desk-top microcomputers which normally handle 12-digit numbers. For secrecy, P and Q must be very large primes in the order of 100 digits. Conse- quently, the method is con- sidered to be suitable only for Public Key Encryption, which is not covered in this article. 10-30 elector mdia octobar 1 987 Measurements of ventricular distances by using ultrasonic techniques by Baki Koyuncu (Physics Department, Kuwait University, Kuwait) A well known technique was used to determine the external dimensions of the heart on any one of its cross-sectional planes under clinical conditions. The circuit described here used sound radiation in liquid and biological media. Sound was transmitted and received by two PZT-4 transducers placed on opposite sides of the sample heart. The time taken by sound to travel through the medium at a known speed V, was measured electronically. The distance between two transducers was calculated from d = Vxt. Under clinical conditions, measurements of distances be- tween surface points of a heart are required. This information is coupled with pressure, blood flow, muscle contraction, etc and contributes towards the di- agnostic picture of the heart. Numerous techniques (U) with implanted radio-opaque markers have been used to assess global cardiac function both before and after operative procedures. Moreover, at- tempts have also been made to quantify the dimension changes by means of indirect methods derived from ven- tricular pressure contours (s_7) . The system developed here employs small oscillating piezoelectric crystals which may be implanted or sutured epicardially. Thus stable, in- dependent alignment of trans- ducers becomes possible and allows precise acquisition of dynamic dimension variations. PZT-4 transducers were placed successfully around the heart to evaluate the ventricular regional function in patients during the experiments. In this study detailed dimen- sional changes were quantified. It was confirmed that the system responded predictably to ex- ternal stimulation as well as alterations in ventricular preload and afterload. Elec- tronic design procedures are presented here together with details of transducer construc- tion. Experiments were carried out on animal hearts for a var- iety of clinical situations. Method The PZT-4 transducers em- ployed during this study were made of barium titarute (Ba Ti 03). They were in rectangular shape with radiating surface di- mensions of 10 mm by 10 mm. Two identical transducers were used. One was for transmission (Tx) and the other for reception (Rx) of sound waves. Each was placed in a plastic casing in such a way that half of its height was outside the case. An air cavity was produced between the casing and the transducer by sealing all the edges of the transducer with a silicon based epoxy glue The whole unit simulated an air backed trans- ducer. Sound radiated from the back radiating surface was reflected back from the air- transducer interface and trans- mitted from the front radiating surface hence doubling the transmission energy. Copper wire electrodes were attached on both surfaces and trans- mission voltages were applied across them. A fundamental res- onant frequency of 300 kHz was chosen for these transducers. The transducers w6re im- planted externally on opposite sides of the heart. Their weights were small enough to justify assuming that they did not damp the motion of the heart. A glass tank with dimensions of 1 m x 0.5 m was used for the ex- periments. The sample was suspended by mechanical clamps in mid air and sub- merged into the tank. The tank was filled with air and it pro- •(•ktot ,ndia October 1987 10-31 1 Fig. 1. Block diagram of the complete system. vided a stable environment free of temperature, air, etc. fluctu- ations. A train of pulse bursts was generated from a gate con- trolled oscillator. Peak voltages corresponding to these pulses were applied across the Tx transducer at its resonant fre- quency. The tranducer im- pedance across its terminals was measured at resonance as 30 S in air. The transmitted pulses had a duration of 5 ps and a repetition frequency of 1.5 Hz. The amplitude of the ap- plied voltage was 9 V; hence the transmitted signal power level was (9/[2) 2 /30 = 0.7 W. Detection of the transmitted sound radiation was carried out by an identical transducer (Rx). The received pulses were amplified and used to generate START. STOP and LATCH con- trol pulses. The block diagram of the com- plete system is presented in Fig. 1. Start pulses indicated the start of the transmission and ac- tivated the counters to count the clock pulses corresponding to the unknown distance. Stop pulses were generated when the transmission was received by Rx. They deactivated the above counters counting the clock pulses. Hence the coun- ters contained a particular number of counts representing the distance between Tx and Rx. A 5 jjs duration pulse was pro- duced at every half cycle of 1.5 Hz. These pulses were termed 'latch pulses’ and used to reset the counters for the next count sequence. The final count at the counter outputs were also transferred to the latch and display sections of the was also transferred to the latch and display sections of the cir- cuit by means of latch pulses. Timing diagrams of the differ- ent pulses are illustrated in Fig. 2. Circuit description: Complete circuitry of the sys- tem is shown in Fig. 3. A FET collector feedback oscillator with its amplifier was used as master clock. A 3 MHz crystal was used along its feedback path to generate 3 MHz sine- wave oscillations. The output was EX-OR gated to convert the oscillations into digital form. These pulses provided the synchronization throughout the system and the control pulses 10-32 elektor mdia October 1987 were derived from them. The oscillator frequency was div- ided by 2 x 10 6 by decade counters and a JK Dip-flop. The frequency divider chain pro- vided a square wave train out- put with a frequency of 1.5 Hz (corresponding to a period of T = 666 fjs). An RC combination with a 1.5 V dc offset differen- tiated the square wave and shifted the resultant above zero volt. A Schmidt trigger gate, Nl, produced the latch pulse with 5 /is duration at every half cycle of 1.5 Hz. The 1.5 Hz square wave was in- verted by N2. A Schmidt trigger gate, N3, gave an output pulse with 5 (is duration at the begin- ning of every 1.5 Hz cycle. Its in- put was the RC differentiated N2 output. These pulses, termed 'start pulses', were ap- plied to the gate terminal of the Tx oscillator (N4 gate) as trigger pulses. The frequency of the Tx oscillator was set to the res- onant frequency of the trans- ducer. The transducer was activated for duration of the start pulse. Hence, a pulse burst of 1.5 cycles at 300 kHz was transmitted with the application of the start pulse. The received pulses at the receiver were time delayed due to the finite dis- tance travelled by the sound. The transmitted pulses also ap- peared at the receiver due to the electronic interference. The inverted start pulses were ap- plied to multivibrators 1 and 2. The first multivibrator's nega- tive edge trigged the inverted start pulse. Its RC time delay was adjusted to 7 jis. Then the output pulse was used to en- velope the unwanted trans- mitted pulse section of the re- ceived pulse train. A 7 ps pulse width set up the limit for mini- mum distance measurement. It corresponded to approxi- mately 7 x 10’ 6 x 1500= 10.5 mm distance. The negative edge of multivi- brator 2 triggered the output of multivibrator 1 and produced a digital high. Later, the output was AND-gated by N6 and N7 with the received pulse train. Consequently, the output of N7 contained only the received pulses corresponding to the distance travelled without any interference present. The out- put of N7 was positive edge triggered by multivibrator 3 and 4 to produce a stop pulse of 5 ps duration. Start, stop and latch pulses were used to control the counters. Initially, a 1.5 MHz signal was applied as the clock signal to the counters. This was derived by dividing the 3 MHz master clock signal by 2. The velocity of sound in the me- dium was taken as 1500 m/s from the literature. Thus, a con- version factor a=l mm/cycle was introduced for the coun- ters. This meant that 1 mm distance corresponded to 1 count cycle of the counters. Therefore, the counters would count whole cycles and the numerical display would give straightforward distance mea- surements in millimeters. The start pulse was applied to D Dip Dop (1) as a clock. When D = 1, the 0 output was set HIGH and the output of N8 copied 1.5 MHz from its input. The out- put of D Dip Dop (2) was also set HIGH when a stop pulse was applied as a clock. Therefore. N8 output was transferred to N9 output and applied to counters as clock signal. D Dip Oops had the inverted latch pulses as their CLR (clear) and PS (preset) inputs. These inputs normally stayed HIGH to let the 1.5 MHz counter clock pulses go through the D Dip Oops. When the latch pulses arrived, D Dip Dop (1) output was reset to LOW. D Dip-Dop (2) output was preset to receive the next count sequence. The clock pulse train between the start and stop pulses corresponding to a particular distance count were applied to the counter stage. Counters were 4-bit binary counters connected in series to give a maximum count of 2" at its 12 outputs. Delayed latch pulses were applied to the CLR inputs of the counters. A delay of approximately 60 ns was introduced to avoid the counters being cleared at the same instant as the D Dip-Dops. Otherwise, the count would be lost before it was latched by the latch circuits. Transparent latches were en- abled by the latch pulses. Twelve-bit latch outputs in binary form represented the fi- nal number of counts corre- sponding to the millimetre distance between two trans- ducers. These 12-bit binary numbers were converted to BCD numbers by binary-to-BCD converters and later displayed by 7-segment display units. A variable capacitor C was in- troduced in series with the master oscillator crystal. It was used to compensate for the fre- quency changes due to sound velocity irregularities in the medium. Exact velocity of sound was calculated as 1550 m/s in the ex- periments. Hence the master clock frequency was adjusted to 3.1 MHz by changing the C value. The new clock fre- quency for the counters was thus 3.1 MHz+2 = 1.55 MHz. As a result, the counter con- version factor (a) remained 1550 m/sT 1.55 M cycle/sec = 1 mm/cycle and 1 mm distance would again correspond to 1 count cycle of the counter. Calibration of the whole system was carried out along the same lines. In the test medium, a pre- cise distance between the Tx and Rx was set by mechanical means. The test medium was Fig. 2. Timing diagram of different pulses and frequencies present at various points in the circuit. blood and the distance was set to 30 mm. The display unit read- out was adjusted by changing the value of the capacitor in the master oscillator until the dis- play read 30. Similar calibration measurements were made with the stationary heart filled with blood. It was found that the displayed numerical values were consistently the same as [ 1 — ®«* J 8 If Jrti n. r ~ H I H TO the mechanical measurements. Hence, the whole system was ready to measure the dynamic distances in the experiments. Experimental Considerations Motion of the heart is a three- dimensional complex motion. The circuit described here would only give the shortest distance along a particular direction between the trans- ducers. The Rx transducer always detected the maximum radiated sound intensity along this direction. The minimum distance measured was governed by the outputs of multivibrators 1 and 2 n 7408 1 5 • 74121 <9 r “ n — ' U. X _ and was set to 10.9 mm. Coun- ting was incremented in steps of 1 and the distance was in- cremented in steps of 1 mm. If the count was more than 0.5 but less than 1, it was approximated to 1 count. If it was less than or equal to 0.5, it was disregarded. Consequently, the maximum uncertainty introduced was 0.5 count corresponding to 500 jim. This error could be reduced by counting more cycles for 1 mm distance. For example, if the 3 MHz master clock frequency was counted, the conversion factor would be 0.5 mm/cycle (2 count cycles per mm) and the above error would be 250 ^m. Further increases in frequency would improve the accuracy of the measurement, i.e. 6 MHz would allow a distance step size of 0.125 mm to be measured. This would give an uncertainty of 0.06 mm (if one could pos- ition the transducer this ac- curately!). For clinical purposes distance measurements with ±500 pm uncertainty were suf- ficient. Hence, no improvement in accuracy was attempted. The maximum measurable distance corresponded to the time interval between start and latch pulses; and it was equal to Vt x 1/1.5 = 0.333 second. If each count represented the time increment tc = 1/1.5 MHz = 0.66 ps, the maximum num- ber of counts between these pulses would be 0.333 sec/ 0.66 jrs^ 5.05 x10 s . Hence, a theoretical distance of 505 m Fig. 3. Circuit diagram of the complete system. •Wttor >ndi« October 1967 1 0 33 would be displayed by the dis- play units. The transmitted power levels would set a more stringent limit on large distance measure- ments. The power received by Rx would decrease rapidly with the increasing distance. Since heart dimensions of 50-150 mm were measured, power con- siderations were not a limitation on the experiments. The system was in no way comparable to X- Ray tomography, emission tomography or some other ad- vanced ultrasonic devices. These are used for non-invasive clinical applications to man and they are far superior in distance measurements to the system here. The system constructed was solely used in the labora- tory to give some notional data of the heart simply and eth- ciently. It could quite easily be used for any biological sample, once the sound velocity in it was known. A large signal amplitude was always present at the receiver terminals corresponding to the minimum path through the heart. Other reflections from the side walls were small com- pared to the main received signal. The circuit did not in- clude automatic gain control in the receiver stage or automatic error compensation (com- paring a number of consecutive readings for the same distance) to keep it as simple as possible Counters were reset by the positive going edge of the delayed latch pulses allowing a new measurement to be taken ! at every 0.66 seconds. The previous read-out re- mained on the display until the information from a new dis- tance measurement arrived. Fi- nally, the accuracy of the measurements was dependent on the factors which influence the speed of sound. The range of the instrument could be ex- tended by increasing the gain of the receiver and the transmit- ter voltage. This was unnecess- ary for the measurements de- scribed here. Acknowledgement The author appreciates the help received from the Physics De- partment of Kuwait University. The work was earned out under | a SDP 111 grant. REFERENCES 1. Newman G.E., Rerych S.K., Journal of Cardivascular Surgery Circulation, 58 Suppl. 2:84, 1978. 2. Rees G., Bristow J.D, N. Engl. ]. Med. 284 : 1116-1120, 1971. 3. Mirsky I„ Cohn P.F., J. of Car- divascular Surgery. Circulation 50 : 128-136, 1974. 4. Rosen Feldt F.L., Gill C.G., Cardiavasc Res 8: 26-36, 1974. 5. Riley S.M.. Blackstone E.H., Surg. Forum 26: 220-221, 1975. 6. Wechsler A.S., Gill C; J. Thorac Cardiovasc Surg. 64 : 861-868, 1972. 7. Bolooki H., Rubinsen R.M., /. Thorac Cardiovasc Surg. 62: 543-553, 1971. A TIDAL GENERATOR FOR ENERGY AND JOBS by Vic French An ambitious plan to produce electricity from a tidal barrage acros the River Severn estuary has been investigated by a special body reporting to the Secretary of State for Energy. The barrage might run from the holiday resort of Weston-super- Mare to Cardiff, though the study also considers an alterna- tive location. Coincidental with the report- submitted by the Severn Tidal Power Group (STPG)— was a government pledge backing further studies in tidal resources to the value of £5.5 million. This includes a con- tribution towards research into a River Mersey barrage with generic studies to take in con- struction techniques and an in- vestigation into the potential of smaller sites around Britain. The Severn scheme investiga- tion and report were financed jointly by the Department of Energy with the STPG, and a group of companies compris- ing Sir Robert McAlpine and Sons, Balfour Beatty, GEC Energy Systems, Northern Engineering Industries (NEI), Taylor Woodrow Construction and Wimpey Major Projects (representing Wimpey Atkins Joint Venture). Among attractions of the scheme are the facts that it would contribute up to 6% of the demand for electricity in England and Wales, would have a life of at least 100 years, and could provide a trunk road across the Severn estuary to link the present and proposed major road networks in south- west England and south Wales, relieving the Severn Bridge. Its generation costs would be comparable to those of the Sizewell B nuclear power station. Second option The study has considered a second option for a barrage ad- jacent to English Stones, a site j some eight kilometres from the Severn Bridge and 36 km up- river from the Weston-Cardiff site. A potential problem there is that fine sediments might af- fect the barrage, and a major in- vestigative study would be re- quired. The capital cost of the Cardiff- Weston scheme is estimated at £5,543 million (January 1984 prices). It could provide 45,000 jobs during the construction An artist's impression of the Cardiff Weston barrage looking upriver. 1 0-34 ,nd,« ocwrtw 19S7 period of seven years, with at least another 22,000 jobs out- side the energy sector. About 1,700 people would be directly employed to operate the scheme, and there would be considerable benefits in the form of industry, housing and tourism. The proposed Cardiff-Weston barrage would have a length of 16.3 km, with an installed ca- pacity of 7200 MW from 192 bulb turbine generators in run- ners of 8.2 m diameter. There would be 48 turbine generator caissons, each 65 m by 72 m in plan, with four turbine gener- ators per caisson and an effec- tive sluice area of 21,600 m 3 . The annual energy output would total 14,4 terawatt hours (TWh), one terawatt hour being a million million kilowatt hours. Siltation studies by STPG have shown that it will be necessary to use empty caissons to close the barrage on either side of the turbine caissons instead of the more normal embankments. They would be watertight struc- tures open at the bottom and containing air under pressure. There would also be 62 sluice caissons and 50 plain caissons. The advantages A total volume of structural con- crete of 3.1 million m 3 would be required. Steel structures have been considered but do not show any cost benefit over concrete. An internal structure of steel might be an advantage but this would need investiga- tion. Plain caissons used instead of embankments are rec- ommended where the seabed level is even lower than 15 metres below the Ordnance Datum level, as this reduces the total volume of materials re- quired for construction, speeds up the time taken for the work, and improves the closure se- quence. The type of turbine generator has been chosen in view of the long operational experience with this particular design. It could be manufactured with the certain knowledge of its performance and installed as a complete package. The 1600 tonne package would be con- structed as a single unit, floated to site on a sea-going barge, and installed in the caisson which could already be in pos- ition in the estuary. This would 1 PRINCIPAL DETAILS OF THE SCHEMES Total length of barrage Cardiff-Weston 16.3 km English Stones 7.1 km Installed capacity 7,200 MW 972 MW Type of turbine generator Bulb Bulb Number of turbine generators 192 36 Runner diameter 8.2 m 7.5 m Effective sluice area 21,600 m 2 5,976 m 2 Number of turbine generator caissons 48 12 Turbine generators per caisson 4 3 Plain caissons in lieu of embankment 50 2 Annual energy sent out (average year) 14.4 TWh 2.8 TWh Capital cost (January 1984) £5,543 million £1,150 million be a considerable advantage, as the plant would be factory tested and partially commis- sioned, reducing the time and manhours required for instal- lation in the barrage. The number of turbine generators used in the barrage, of course, controls the ’’energy capture” of the scheme, but would be restricted by the available depth of channel in which they could be located without the need for expensive dredging. Variable speed DC generation has been considered in the quest for an improvement in economy, but the gain in energy produced was smaller than expected, and the cost of a high voltage DC system would not be recovered by increased revenue or significant oper- ational benefits. Fixed speed generation and AC transmission have therefore been chosen. I Not a problem Re-inforcement of the Central Electricity Generating Board (CEGB) transmission system would be required to ac- commodate the output from the barrage. This would be undertaken by the CEGB and financed from barrage revenue. Intermittent output from the barrage would not pose a major problem as power stations have to contend with much larger power variations in consumer demand. In order to increase the net value of annual energy put out by an ebb generation barrage, the STPG considers that there would be a net benefit in pump- ing into the basin at neap and mean tides. There is a proposal for a smaller schema with a barrage to be built some eight kilometres downstream of the Severn Bridge. This too could carry a trunk road across the Severn estuary to link Wales with southwest England. The cost of this English Stones scheme would be £1,150 million (January 1984 prices). Bulb turbine generators would also be used for this scheme, with 36 installed in 12 caissons, each 63 m by 50 m in plan. The diameter of the turbines would be 7.5 m each with a rating of 27 MW and a total installed ca- pacity of 972 MW. There would be 42 sluices in all, of which 30 would be 12 m x 11 m and 12 would be 12 m x 14 m. Ebb generation with flood pumping would be used again here, giv- ing a firm power contribution of 250 MW and an average annual energy output of 2.8 TWh. Needs of shipping Barrage construction would be very similar to that at Cardiff- Weston although embankments would complete the barrage on each side of the turbines and sluices. In both cases consideration would have to be given to the requirements of shipping. It is suggested that two alternative lock sizes should be con- structed, one for vessels up to 6.000 dead weight tonnes and one for larger ones of up to 25.000 dwt. The locks would be situated between sluice caissons on the Welsh side. This takes into consideration the prevailing wind and current conditions expected when the scheme is complete. The STPG considers that the larger scheme between Weston and Cardiff would be a great asset to the United Kingdom, with its potential for creating employment and the fact that it would produce virtually free energy as an insurance against unpredictable increases in primary energy costs. Tidal power is also non-polluting to the environment. elektor India October 1987 1 0’35 FILTERS: THEORY & PRACTICE — 2 by A.B. Bradshaw Fundamental sections from which more complex ones are built are called prototype filters. The majority of filters used are high-pass, low-pass, band-pass, or band-stop. All of these are usually made up of low-loss reactances connected in T, n, or L form as shown in Fig. 1. Practical filters are nor- mally designed as a combi- nation of these configurations. In the following, the reactance, i.e., the imaginary part of a com- plex impedance, is designated by X, which is equal to 1/coC or oX or a combination of these. Low-pass filters In a correctly terminated low- pass T filter, see Fig. IS: Zot - i'Zi Zz + Zi/4 - \]X- jXi - X\l\ which can also be expressed as Zm = j r^(X/4 _ TX2) [20] If X, and (X,/4+Xz) are of op- posite sign, Zot is resistive and the filter draws power: it is can also be evaluated from Eq. operating in its pass-band— see [19]: Fig. 17. If Xi and (X,/4+Xz) are of the same sign, Zot is reactive and coshy = 1 -t- — the filter reflects power: it is operating in its stop-band -see For the T sec(ion Fig. 17. In a low-pass n filter— see Fig. 16, Zot and Zon are related CQS j l _ j_ w 2 LC by 2 COShy = 1 — — -jr-— u 7n _ _ z,z 2 _ jxxz Zm j\XWU4+Xz) but since y = a+jp, cosh (o+;j?)=coshacosh;/3+ sinhasinh;/? [23] _ j l X \Xt _ — Z’Z; j2i] 1 Since, cosh;/) = cosjl Zm Zot j anc j sinh;/)= jsinj) | Eq. [23] becomes Since X< and Xz are of opposite ! sign, their product is a constant, coshocos/) +/sinht>sin/3 = so that CONSTANT in which Zot varies as in the previous example— see Fig. 17. The value of fc may be deter- mined from an inspection of the characteristics in Fig. 17, but Since the right-hand term in [24] does not contain an imaginary part, the expression can be split into coshocos/3= 1— ^ (real part) O sinosin/)=0 (imaginary part) Considering the real part, in the pass-band the attenuation is zero, so that a=0, and cos(i=l— - Inserting the two maximum values of a cosine curve, i.e„ + 1, in this expression yields From these, the two cut-off fre- quencies can be determined: 10-36 eiefctor India October 1 987 The phase angle, p, can be found by inserting the value of fc [26b] into [25] to give cosfl = 1— 2(///c) 2 so that p=cos '[l — 2(f/fcf] radians[27] Expression [27] is shown dia- grammatically in Fig. 18. In the stop band /J=n, so that cos/! = — 1. Inserting this in [24a] gives cosho — 1 2 so that o=cosh ’[2 (l Kef - 1] nepers [28] where o is the attenuation in the stop band. This expression is shown graphically in Fig. 19. In a low-pass T filter, Z\ = jwL and Zi — \/jwC, so that Z\Zi - L/C. Inserting this in Eq. [5] gives [291 When /=0, Z«r=][L/C When f— fc, ZoT=l/^=0 r c c Therefore, over the pass-band from /=0 to f=fc, Zor moves from yLIC to zero ohms. Since the tt network is related to the T type, it may be concluded that ZOn — ZxZt L/C Zm ]/LIC - w‘L ‘/ 4 When /=0, Zo*=]/ L/C When f=fc, [301 - L/C - - ijL/C - L/C The variations of Zot and Zov are shown in Fig. 20. The basic design equations can be obtained from the foregoing discussions, but are summar- ized here for convenience’s sake: they apply to T and n sec- tions alike. Zo = Ro = 1 L/C fc = 1 /jLC L = CRo 1 C — 1/ 7i Ro fc High-pass filters In similar vein as the consider- ations on the low-pass filters, the reactances and impedances in a high-pass T filter as shown in Fig. 21 are X, = \/wC or Zi=l/yo)C and Xz=oiL or Zi = jwL so that XK4+Xz = wL - l/4a ,C A graphical representation of these reactances is shown in Fig. 22. Substituting the impedance values given above into Eq. [19] yields C0Sh ' =1 -d£c By a similar consideration as before, coshocosfl =1— „ * „ 2 u’LC In the pass-band, o=0, so that cosho =1, and cos|3=l— 1 2 c o'LC [31] Substituting the limits of + 1 for cosp in [31] gives + 2 ofLC and 2nd<* octotoer 1 987 10-39 33 34 TERMINATING SHARP CUT ONE OR MORE SHARP CUT TERMINATING HALF SECTION M0.3 - MO. 4 CONSTANT K M0.3 - MO. 4 HALF SECTION MO. 6 SECTION OR LARGE SECTION M0.6 VALUE •M’ SECTION 87134*11-34 shown in Fig. 33 for both a T and a n half section. Low-pass and high-pass filters are designed to a given specifi- cation by combining Af-derived terminating sections with small- value M sections, and either constant-/: or large-value M sec- tions in the middle so that the attenuation far from the cut-off frequency can be made large. A typical cascade is shown in Fig. 34. The foregoing covers the basic principles of the image parameter network theory. Band-pass filters, both con- stant-^ and M-denved, can be designed with the aid of this theory, but the computations tend to become cumbersome. Band-pass filters may be con- structed by cascading low-pass and high-pass sections, particu- larly when large bandwidths are required, but this method presents difficulties with true band-pass designs. None the less, design equations for a constant-/: and an Afdenved band-pass filter as shown in Fig. 35 are given here without proof: ft ft ft — ft--2Nfc/y|l— M')= bandw idth 1 (1 - M 7 ) In modern network theory (syn- thesis techniques), tables are available that enable the design of low-pass, high-pass, and band-pass filters from AF up to about 500 MHz to be under- taken with the aid of a hand- held calculator only. The concluding part of this article will be published in next month’s issue. 10-40 elektor mdia October 1 987 UNIVERSAL EPROM EMULATOR Any EPROM can be emulated by a RAM with double access: one for reading, and one for writing. The circuit presented here is situated between a host computer and the target system whose resident EPROM software requires fast and efficient editing, that is, without the use of an UV lamp and an EPROM programmer for testing the effect of any small alteration. An EPROM emulator can offer a significant time saving to pro- grammers engaged in writing, debugging, or upgrading resi- dent EPROM software. Virtually every computer operator knows that even a single wrong bit in an EPROM may require the de- vice to be taken from its socket, erased with ultra-violet light, verified for complete erase, and entirely re-programmed. Ob- viously, this is a time consuming procedure that readily ends up in one or more of the EPROM terminals breaking off. The EPROM emulator presented here enables modifying the EPROM contents while this is used in the target system. A separate (host) computer is used for editing and filing the contents, and for downloading it into the target system until this runs to satisfaction. RAM for EPROM An EPROM emulator is essen- tially an autonomous block of RAM which can be accessed from two sides simultaneously. For the host system, i.e., the external computer used for editing and downloading the program, this block of memory offers read and write access, for the target system read access only. The EPROM emulator therefore comprises a buffered block of RAM whose write enable line can be blocked to simulate the function of a ROM, inserted in the place of the EPROM whose contents re- quire correction or alteration. The EPROM so emulated con- tains one or more programs or data blocks (look-up tables and the like) that are essential to the operation of the target system. The writing and/or correcting of the EPROM contents is car- ried out on the host system, which controls and loads the EPROM emulator via a standard serial (RS232) or parallel (Cen- tronics) interface. The target system may be any 8-bit, micro- processor-controlled system, or, indeed, another microcom- puter. It is even possible for the host and target system to form part of one and the same com- puter, which can then modify some of its ROM or EPROM based software via the serial or parallel port. Two EPROM emulators can be operated in parallel to enable working in a 16-bit system. When only one parallel or serial port is available on the computer, the emulators can be connected in turn for alternate editing, filing and downloading of the least significant and most significant databytes. Access from two sides The basic operation of the EPROM emulator is shown schematically in Fig. 1. The EPROM whose contents re- quire editing is removed from its socket in the target system, and its place is taken by a header connected to a length of flat ribbon cable carrying the data, address and control lines available in the target system to the EPROM emulator. In this, the address bus is connected to a buffer controlled exclusively by the emulator, while the data bus is connected to a buffer controlled exclusively by the target system. The other side of the buffers is connected to a 32 Kbyte RAM, in which the emulator CPU— a Type 8748H here— places the datawords re- ceived from the host computer. To avoid all misconception, it is necessary to keep the functions of host system, EPROM emu- lator, and target system quite separate. When a complete block of data has been received by the CPU in the emulator, it arranges for the address buffer between the 32 Kbyte RAM and the target system to be enabled, and its own data and address Bleklor md'aoaober 1987 10-41 IK* 8 EPROM 87138 -0 Intel's 8748H/8035H/8749H/8039H microcontrollers Universal EPROM Emulator Technical characteristics: ■ Emulates EPROM types 2708, 2716, 2732, 2764, 27128 and 27256. ■ Direct communication with the target system via a DIP header inserted in the EPROM socket. ■ Serial and parallel IRS232 or Centronics! input tor downloading EPROM data from the host computer ■ Serial data format: 1 start bit, 8 data bits, 1 or more stop bits. 4 switch selectable baudrates: 1200, 2400, 4800 and 9600 ■ Supports 3 file transfer formats with checksum — Intel — Tektronix — Motorola Binary transfer without checksum. ■ Visual indication on DATA and READY {transfer complete) line. ■ Audible signal for error reports. ■ Fast, cost effective and easy to use. Introducing the 8748H microcontroller. In view of its specialist nature, Intel's microcontroller Type 8748H has not yet been the subject of an article in Elektor India, although it has been on the market for some years already. That shortcoming is rectified in the present article. The 8748H and Intel’s more recently introduced MCS51 series (de- scribed in Single-chip microcontrollers, elsewhere in this issue) are firmly aimed at electronics specialists, and will form the basis of a number of articles to be featured in forthcoming issues of Elektor Electronics. The 8748H affords good introductory experience with these ready- programmed microcontrollers. It is a less complex and less ex- pensive controller than, say, the 80S1, but it is none the less perfectly suitable for a number of small-scale applications, such as the EPROM emulator presented here. The 8748H is the EPROM version of the mask-programmable 8048, which has found numerous applications in computer keyboards and industrial control systems. Neither the 8748H nor the new MCSS1 series can be programmed with an ordinary EPROM pro- grammer. but can only be purchased ready programmed from Elektor Electronics or its agents. These devices, therefore, signal the end of the publication of hexdumps, source listings, and other detailed information on the control program. I •7134 - I Fig. 1. Illustrating the basic operation of the EPROM emulator. bus to be disconnected from the RAM. Control line WE (write enable) of the RAM is deactivated, while CE (chip enable) is left active. From then on, the relevant area of the 32 Kbyte RAM functions as a read-only memory block in the target system, which gains ac- cess to the "EPROM” contents with the aid of lines OE (output enable) and CE via the 28-way flat ribbon cable. System control: the 8748H Briefly recapitulating the foregoing, the EPROM emu- lator can be considered a quasi- intelligent EPROM which, apart from its data and address bus, has a serial or parallel interface for ready and fast external pro- gramming. The circuit diagram of the pro- gramming tool appears in Fig. 2. At the heart of the circuit is the Type 8748H microcon- troller, ICi. When the RESET key, Sio, is pressed, the CPU reads the position of S9 to select between parallel and serial data transfer. The file transfer mode, EPROM type, and serial data speed is read from the con- figuration of DIL switches Si- S8— see Table 1. The parallel, Centronics compatible, input is complete with 8 data inputs plus t he associated strobe line, STRB, and 2 handshaking signals: ACK and BUSY for inter- faces activated with the aid of a negative or positive level tran- sition respectively. The non- used outputs PE (paper empty). INPUT PRIME RET, and FAULT are forced to the inactive logic level, so that virtually any com- puter should be able to com- municate with the EPROM simulator as if it were a standard printer. It should be noted the Ki is a 36-way header on the PCB for connecting to a Cen- tronics socket on the EPROM emulator. The correct pin con- nections between these are automatically made with the aid of a length of flat ribbon cable and a 36-way IDC socket. Therefore, the pinning of Ki is not identical to that of the Cen- tronics socket. Since the processor is not fast enough for reading the data on the Centronics input, octal latch IC? is clocked with the STRB pulse for intermediate data storage, while the bistables in IC« generate the ACK signal 10-42 efafclor indis October 1 987 when output P1.7 on the CPU goes high, signalling readiness for reception of a new byte. The presence of a new byte in latch IC7 is signalled to the processor by the negative transition of the inverted BUSY signal, which is applied to input INT, and used for lighting LED D2 also, en- abling the user to verify recep- tion of data both in the parallel and the serial mode. CPU input TO is grounded via S9b when the parallel mode is selected. In the serial mode. Ti and Di convert the RS232 levels on the RxD line into SV pulses for driving the INT input on the CPU. It should be noted that the absence of handshaking on the serial input necessitates the use of a number of "zero-modem” wire links on the connector at the host computer side, and this will be reverted to under Con- struction. RS232 handshaking lines are omitted to keep the serial interface simple, without compromising the data transfer speed, which is still fairly high at 9,600 baud maximum. When an error condition arises, the processor arranges for buzzer BZi to be actuated via output Pl.l and MOSFET T2. The ready LED Dj, is illumi- nated by Tj when the processor activates its P1.2 output. A single RAM chip, IC2, caters for the entire 32 Kbyte memory to enable programming all the EPROMs in the 27XXX series without running into problems regarding the address con- figurations. Three buffers are provided for accepting the bus signals from the target system: ICi and IC< for the address bus, and ICe for the data bus. The outputs of these buffers can be switched to the high impedance state by making input El or E2 logic high. The function of ICi is ap- parent from the signal applied to pin 11: ALE (address latch enable) is the demultiplexing signal for the databus (D0-D7) and the LS address bus (A0-A7) which share pins 12 to 19 incl. on the 8748H controller. The target system can only read from the EPROM when IC» and ICs are activated by the high level on processor output P1.2. In this condition the RAM can place its data onto the databus, smce OE is low together wit E2 and El of the buffers, while demultiplexing latch ICa is switched to the three-state mode. The target system can ac- tivate IC6, and hence read the RAM, by pulling the OE and CE lines on the EPROM socket low. The rather unconventional cen- tral clock frequency of 9.216 MHz (Xi) is needed for the timing on the serial input chan- nel, since the 8748H lacks an ACIA based asynchronous communication port. In the present circuit, the processor’s interrupt facility is used for reading serial characters. Reception of a serial dataword commences with an interrupt caused by the negative tran- sition of the start bit pulse. When half the start bit period has lapsed, the 8748H starts a counter to introduce a delay corresponding to the period of the start bit. This period depends on the baudrate set with S.-S7. When the delay has lapsed, a new interrupt is generated when the counter counts out. This happens when half the period of the second bit has lapsed. The CPU reads the logic level on the R x D line via Ti and restarts the counter for another bit period, ensuring enough time for processing the received bit, ie., using it for composing the complete data- word and organizing the hexa- decimal file in the memory. This process continues until the last bit of the last dataword has been read into the emulator. The maximum bit rate so achieved is 9,600/s without the use of handshake signals. 533 ? 3?3 el«ktor india ociober 1987 10-43 igaaaaaaiaaaiaFiiaFil RAM Read/Write Address -EPROM" Read Address 2708 A0...A9 2716 A#...A10 2732 A0...A1 1 2764 A#...A12 27128 A#. .A 13 27256 A6...A 14 Fig. 3. Memory configurations for the various types of EPROM that can be emulated. The CPU clock frequency is de- termined by the bit period and the internal clock division fac- tors, 15 and 32, of the 8748H. The EPROM emulator draws about 200 mA from an external 5 V supply, which will be part of either the host or the target system in most cases. It is, of course, also possible to build a simple, 7805 based, power supply for the emulator. Addressing Figure 3 shows that substitution of the EPROM in the target system by an external block of RAM requires consideration of the implications of this at the ad- dress decoding level. This is briefly discussed in the follow- ing four points. 1. If the emulated EPROM has a capacity of less than 32 Kbyte, the corresponding RAM area in the emulator is always located below the upper bound of the 32 Kbyte area extending be- tween OOOOh and 7 FFFh. A Type 2764 8 Kbyte EPROM, for example, is emulated with the aid of memory area 6000 h ( lowest EPROM address) to 7 FFFh (highest EPROM ad- dress). Therefore, Fig. 3 dis- tinguishes between the read / write address area of the RAM, and the read-only address areas in the RAM considered EPROM by the target system. All oper- ations in the memory are ef- fected by the 8748H alone, and are invisible to the user. 2. The size of the memory area must always correspond to that of the emulated EPROM. In practice, this means that a 27128, for instance, should not be emulated with the settings of a 2732, or vice versa. The con- tents of the emulated EPROM are only verified when certain conditions relating to the data transfer are satisfied— this will be reverted to in the section on file formats. 3. Non-used address lines should be left unconnected or made logic high in the target system. When, for example, a 2764 is emulated, the address lines used are A0-A12 incl. (see Fig. 3). The socket pins carrying address lines A13 and A14 should then be made logic high, or left unconnected. 4. In addition to +5 V, the now obsolete Type 2708 needs a + 12 V and - 5 V supply voltage, both of which may not be car- ried by pins 21 and 19 of the EPROM socket that receives the header from the simulator. When the emulation is finished, the relevant connections should be restored before fitting the (re-programmed) 2708. File formats The contents of the emulated EPROM are transferred via the parallel or serial interface. The bit rate on the serial channel, the EPROM type, and the file transfer format are set with DIP switches Si-Ss as shown in Fig. 6. Four file transfer formats are supported by the present EPROM emulator: binary, Intel, Motorola and Tektronix. The least complex of these is the binary format, in which the bytes for the emulated EPROM are transferred sequentially, starting with the lowest and ending with the highest one. The operating system in the EPROM emulator waits for the last byte in the 1, 2, 4, 8, 16 or 32 Kbyte large block of data before the target system can gain access to the RAM. The ready LED is illuminated when reception is complete. The binary transfer format has no verification procedure(s), but is faster than any of the other 3 for- 4 INTEL Intel lec 8/NOS Format address 2 hexadecimal characters = 1 byte 16 databyles (example) checksum ol Mock ‘ 1 10 , 00O0 1 0C 'FF FF FF Ff FF FF FF FF FF FF FF FF FF ff FF FF 0C ik 10 0010 OO FF FF FF FF FF FF FF FF FF FF FF FF Ff FF FF FF F0 xx 10 0020 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF E0 xx 10 0030 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF DO xx 10 00*0 00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF CO xx^ ,00. 0000 .OLTF,! — test block T checksum of last block Mock type (M; data 01: end) number ot databytes (hex) xx = ignored characters (CR-LF) MOTOROLA Kxorciser Format TEKTRONIX Hexadecimal Format neae address X. 16 databyles (example) checksum of last block X 10 01 'FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF £0 xx / 0010 10 02 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF Ff £0 xx 0020 10 03 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF EO xx 0030 10 0* FF FF FF FF Ff FF FF FF FF FF FF FF FF FF FF FF EO xx / 0040 10 05 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF E0 xx^ 0000 ,00, 00,13— last block checksum ot address indication and count byte data blocks number ot databytes (00 = end ot block, hex) ignored characters (CR-LF) header number ot databyles ♦ 3 (hex) 16 databyles (example) checksum ol Mock X blocks t 13 0000 FF FF FF FF FF FF FF FF FF FF FF FF FF FF Ff FF FC xx| 13 0010 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF EC xx _ data 13 0020 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF U xx “ 13 0030 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF <_C xx 13 00*0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 6C xx 03 0000 FC~3— Iasi block checksum of last block Comparative example ol data transmission: 1 0 1 1 1 1 0 1 Databyte BOh m binary lorrr at (1 byte pet dal a word; ASCII "B“ * -.-Hf, 01000010 Dataword BDh in non-binary format (2 hexadecimal numbers per dataword) ASCII “D" = —hcx 0 1 0 0 0 1 0 0 xx ■ ignored characters (CR-LF) Fig 4 Examples showing the essential characteristics of the various file formats supported by the EPROM emulator. Note that neither the block size of 16 bytes, nor the sequential addressing method of the blocks is imperative. 10-44 elefctor indie October 1 987 Fig. 5. The printed-circuit board for the emulator. 6 Parts list Resistors (±S%): Rt;Ra;R9|Rio;R7r = 10K Rj;Rt = 330R Rs;R4;R2i;Rm;Rw = 4K7 Rj;R» = 1K0 Rn. . . Ru incl.;Rn. . . R 2 i ind. = 10K SIL networks with 8 commoned resistors. Capacitors: Ci;Cs=3n3 C2;Ci- 33p C«= Ip: 16 V; axial Cs=10yr; 16 V; axial Cr. . .Cio ind. = lOOn Semiconductors: Di;D. .Du - 1N4148 D 2 = red LED Ds= green LED T i = BC547B T2 ;Tj = BS170* ICi - 8748H (available through the Readers Servicesl. IC 2 - 62256 or 43256 I32K ■ 8 CMOS static RAM) ICi = 74HCT573 or 74LS573 IC.;ICs;IC.-74HCT541 or 74LS541 ICr = 74LS374 IC« = 74LS74 ( \ ELEKTOR EPROM EMULATOR v. J r sv n x e \ DAT* O SI S2 S3 EPROM S4 S5 FORMAT 0 0 0 2706 0 o INTEL 0 0 - 2716 o - BINARY 0 - 0 2732 - 0 MOTOROLA o 2764 TEKTRONIX -00 27126 - 0 - 27256 S6 S7 BAUDRATE 0 0 1200 0 - 2400 - o 4800 9600 O = OPEN - = CLOSED S8 = NC J V. READY — O RESET O RS232 — CENTRONICS J Fig. 6. Suggested front panel for the EPROM emulator (foil is NOT available through Readers Services). True width is 178 mm. mats for updating or loading all or part of the contents of the emulated EPROM. Active buzzer Bzi sounds briefly to in- dicate that the emulator is fed with more data than can be held in the selected EPROM type- no account is taken of the ex- cess bytes. The EPROM emu- lator should be reset before downloading a new file. Con- trary to the standard adopted for the file transfer formats de- scribed below, the binary for- mat does not require data to be converted into hexadecimal characters. When the EPROM emulator is set to operate with the file transfer formats adopted by Intel, Motorola or Tektronix, the target system can only gain ac- cess to the emulated EPROM when the 8748H has received and recognized the marker end of file record, which, however, need not necessarily signal the end of the EPROM contents. In fact, these formats permit modification of only a number of bytes at EPROM addresses that can be specified by the protocol. This effectively speeds up the downloading process because only parts of the memory to be modified are involved. A further advantage of the above formats is the use of a checksum, which enables veri- fying the reception of correct data. The error buzzer sounds intermittently when a discrep- ancy is detected. After recep- tion of the end of file record marker, the EPROM emulator verifies the contents of the "EPROM”, but the buzzer keeps sounding until the reset key is pressed. Reports of discrepancies between the EPROM data on the host system and those in the emulator's RAM are due either to errors in the transmission, or— less likely— to a checksum error in the original file. In the former case, correct data transfer is readily achieved by once more sending the relevant block to the emulator, while in the latter case an investigation is needed into the operation of the checksummer on the host sys- Miscellaneous: Xi =9.216 MHz. Si . . S« incl. = DIP switch block. Si= miniature DPDT switch. S 10 - miniature push to make button. Bzi = self-oscillating 5 V buzzer. Ki= double-row angled 36-way PCB header. Mating I DC socket for Ki. 36-way IDC Centronics socket. K 2 = 28-way 1C socket with turned pins. 2 off 28-way DIL headers for press-on (IDC) connection on flat ribbon cable. PCB Type 87136 (available through the Reade rs Services). Suitable ABS enclosure. Battery-mains socket and plug for external 5 V suppy (e g. Roca 2.5 mm'l. Note: the front panel foil for this project is not available through the Readers Services. * Available from Cricklewood Elec- tronics Limited (see p.11) aleLlor mdia oclobar 1987 1 0 - 45 tem, since the error may well persist no matter how often the block is retransmitted. Examples of the 3 non-binary file formats are shown in Fig. 4. Each byte is transmitted as 2 hexadecimal numbers, i.e., ASCII characters. Example: dataword BDh is transmitted as 42h followed by 44h, which are ASCII codes for B and D re- spectively. Data is organized as records consisting of 16 bytes, in accordance with a standard- ized conversion of each data- word in two hexadecimal characters. When a program for supporting these formats is not available for the host computer used, formatting routines need to be written starting from the guide lines given in Fig. 4. The address transmitted at the be- ginning of each block is that of the first byte. The header (start character) is not the same for the three formats. In the Intel and Tektronix standards, the count byte gives the number of bytes contained in the block, and is, therefore, 00h in the final block. In the Motorola format, the count byte is the number of bytes in the block plus 3. The checksum in the Intel standard is the 2's complement of the sum of the preceding bytes, in- cluding the count byte, address and data. In the Tektronix for- mat, the 2 checksums trans- mitted for each block are the 8-bit, modulo-256 sum of the preceding 4-bit hexadecimal numbers. Motorola uses yet another verification procedure: here the checksum is the l's complement of the binary sum of the count byte, address bytes, and databytes. The end ol the block marker is 01 h (instead of OOh) in the Intel mode, and S9 h ( instead of S1 h) in the Motorola convention. Characters re- ceived after the checksum of the block, and before the header of the next block, are simply ignored, and can not upset the file transfer. In the following example it is as- sumed that the Intel format is used. Each line of 16 databytes results in 43 ASCII characters, followed by the expletive CR/LF sequence, i.e., 45 bytes in all for the transfer. The time needed for transferring a memory area of n bytes at a bit rate B is therefore calculated from (n/16)x45x(10/S) [s]. Using the Intel format, a file 10-46 india October 1 987 7 5V 5V ©- mi i mu 1 1 1 1 i hi 1 11 IC1 0 Too 1 Fig. 7. Build this alternative clock oscillator circuit if a 9.216 MHz crystal is unobtainable. Table 1. c K1 II signal C K1 signal 1 1 DATA STROBE 19 2 2 3 DATA 1 20 4 3 5 DATA 2 21 6 4 7 DATA 3 22 8 5 9 DATA 4 23 10 6 11 DATA 5 24 12 GND 7 13 DATA 6 25 14 8 15 DATA 7 26 16 9 17 DATA 8 27 18 10 19 ACKNLG 28 20 11 21 BUSY 29 22 12 23 PE = "0" 30 24 INPUT PRIME RET = "O'' 13 25 "r 31 26 NC 14 27 NC 32 28 FAULT = "0" 15 29 NC 33 30 NC 16 31 NC 34 32 NC 17 33 NC 35 34 "1" 18 35 NC 36 36 NC Note: C = Centronics connector. NC = not connected. i Fig. 8. Inside view of EPROM emulator. consisting of 4096 bytes can be transmitted in 12 s when the baud rate is 9,600. For the binary format, the time required is simply the EPROM capacity multiplied by 10/n, i.e„ 4 s for 4 Kbytes at 9600 baud. Construction and use in practice The component mounting plan for the double-sided, through- plated circuit board is shown in Fig. 5. As already mentioned, the pinning of connector K. enables ready connection to a Centronics socket via a 36-way IDC header and a length of flat ribbon cable— refer to Table 1. The Centronics or RS232 cable between the simulator and the host computer should not be longer than about 1 metre. The connection between the emu- lator (Kz) and the EPROM socket in the target system is made with the aid of a 20 to 30 cm long flat ribbon cable ter- minated at both ends in a high quality 28-way DIP header. It is possible to omit Kz and solder the header straight into the rel- evant holes in the PCB, It is ad- visable to check the correct connections between the sys- tems, and to mark pin 1 of the target header in write paint to avoid all confusion. All parts are soldered onto the PCB, except the 2 LEDs, Sz, Sio and the self oscillating buzzer. Diodes D«. . .Du incl. are fitted vertically with the cathodes pointing upwards and com- moned by a length of horizon- tally running wire. The same mounting method applies to Rzs, Rz 9 and Rm, and also for Ri9...Rz« incl. and Rn...Ri8 incl. if suitable SIL type resistor networks are not available. ICz and IC« should be low power Schottky (LS) types in view of the possibility of then inputs re- maining unconnected. These 2 ICs can be omitted if it is not in- Fig. 9. A prototype of the EPROM emulator used in conjunction with an Amstrad PC1512 host computer. tended to use the parallel input of the EPROM simulator. All other integrated circuits can be LS or HCT types. Make sure that ICr and RAM ICr are fitted with the correct orientation on the PCB. The power supply con- nection to the board is made either direct in relatively strong wire, or via a 2-way edge con- nector with screw terminals. As to the enclosure that houses the EPROM emulator, the photo- graphs in this article should give some idea of the practical realization. Whatever housing is used, make sure that the data and error LED are mounted such that their visibility is en- sured from relatively far. and also that Sio is within easy reach. It is recommended to have the DIP switches protrude from the top panel to enable rapid changes of the settings. Figure 6 shows a possible layout for the pront panel of the emulator. It was already noted that the 9.216 MHz crystal may be a difficult-to-find component. Fig. 7 shows a suggestion for an alternative clock oscillator based on a 18.432 MHz crystal. It should be noted that this cir- cuit can not be located on the PCB for this project, and therefore needs to be built sep- arately on a piece of Veroboard. It is important to have both the emulator and the target system powered when the connection between them is installed or removed. As already suggested, a zero- modem configuration is used for the handshaking sigals on the RS232 interface if this is used for loading data into the EPROM emulator. Output signal RTS [request to send, pin 4) is connected direct to input CTS C clear to send, pin S), and the same goes for DTR (data ter- minal ready, pin 20) and DCD ( data carrier detect, pin 8). If necessary, DSR ( data set ready, pin 6) is connected to DTR- DCQ These connections should enable the RS232 inter- face to function as if there were real handshaking signals. Whatever computer or com- puter-based system is emulated with the present EPROM emu- lator, both units should be pow- ered before being intercon- nected. Initialize the EPROM emulator by pressing the reset key before transferring a new data block or file. The initializ- ation has no effect on the RAM contents, but informs the 8748H that a new block of data is immi- nent. Also do not forget to press reset after making any change in the DIP switch settings. A 8748 based serial EPROM programmer will be described in a forthcoming issue of Elektor India. EW PRODUCTS • NEW PRODUCTS • NEVi The Protel PCB Design Package An enhanced version of the popular low-cost PCB design package— Protel-PCB— is now available from UK distributor Engineering Solutions Limited. Version 3.0, pric.ed at £799.00, features netlist capability from compatible schematic software, Track/Layer swapping, ad- ditional text sizes, power and ground planes, NC drill support and EGA support for 640 x 350 pixel display. Protel-PCB will design PCBs as large as 32 x 19 inches on six track layers to a one-thou grid resolution and additionally of- fers a range of features normally found only on expensive work- station design systems. Other features include four track widths, six pad sizes, four edge connector pad sizes and two DIP pad sizes to suit a wide variety of applications. The program generates multi- coloured checkplots, camera- ready artwork, Epson check printout and Gerber-compat- ible files, in addition to NC drill support. A fully interactive evaluation disk is available from Engineer- ing Solutions for 25.00. Engineering Solutions Limited King's House, 18 King Street, Maidenhead, Berkshire SL6 1EF. Telephone: (0628) 36052 Telex 849462 TELFAC G Fax: 0628 74928 (3654: 13:F) elefctOf India October 1987 1 0-47 ACTIVE PHASE-LINEAR CROSS-OVER NETWORK The ideal cross-over network is free of phase-shift, resulting in optimum pulse performance and radiation pattern. Although the ideal is not yet within reach, the work of Stanley Lipshitz and John Vanderkooy enables it to be approached very closely. The most serious problem with ordinary cross-over filters is best illustrated with reference to a two-way system. This con- sists of a low-pass and a high- pass filter. One of the proper- ties of a low-pass section is that it causes a time-delay of the signal. A high-pass filter on the other hand causes an acceler- ation of the signal. These ac- tions result in a number of complications at the cross-over point: (a) the signals from the two sec- tions partially cancel one another; (b) the strongly varying phase shift between the two sig- nals adversely affects the radiation efficiency of the overall system; (c) the radiation pattern becomes frequency depen- dent. Some years ago, Stanley Lipshitz and John Vanderkooy pub- lished a series of papers (’• 2 ' 3 ) that have laid the foundation of the so-called phase-linear cross-over network. Basically, the phase-linear net- work uses a low-pass section that also provides a high-pass characteristic with the aid of a time-delay and subtraction cir- cuit. True, the time-delay is not constant over the entire fre- quency range, but it varies only slowly; moreover, there are no phase differences between the two output signals, even near the cross-over frequency. A block schematic of a two-way, as well as a three-way, system based on the work of Lipshitz and Vanderkooy is shown in Fig. 1. It should be emphasized that the time-delay is an essen- tial facet of the design. There are filters that make use of the subtraction method only, but these do not exhibit phase linearity. 10-48 elefctor mdia octotoer 1 987 1 a) Fig. 1. Basic phase linear filter: (a) two-way, and (b) three way. Fig. 2. Vertical radiation pattern: (a) of system with conventional network, and (b) of system with phase linear network. 87109-1 A customary fourth-order low- pass filter in the upper branch provides the normal low-pass performance. The delay, t, is designed such that it has exactly the same phase behav- iour as the low-pass section, and functions as an all-pass sec- tion. When then the output signal of the low-pass section is subtracted from the delayed signal, the result is a high-pass characteristic that has the same phase behaviour as that of the low-pass filter. Summing the two signals results in a perfectly straight line. The set-up of a three-way sys- tem— see Fig. lb— is a little more complicated, because an additional low-pass section has to be provided in the centre limb to obtain a band-pass characteristic for the middle frequency loudspeaker. This additional section must be com- pensated by a second delay, n. Thus, in a three-way system, the ti circuit simulates the time delay of the usual bass filter, while the t* delay simulates the delay of the low-pass filter in the middle-frequency section. The vertical radiation pattern (polar response) of a conven- tional loudspeaker system is shown in Fig. 2a. The disper- sion is fairly small in the region where both speakers provide a signal. The spread also varies with frequency, which causes the lobe to either tilt or sag. The pattern of the phase-linear system in Fig. 2b shows that the lobe is much broader and points forward at all fre- quencies. In all this it is as- sumed that the acoustic centres of the loudspeakers lie on a ver- tical line, otherwise the pattern deteriorates. A practical network In a practical network, it is not possible (at least with an ac- Suhtr. filter Fig. 3. Amplitude vs frequency characteristic of a three-way phase-linear network. r?ooi f tool ig, « Fig. 5. Printed circuit board of the phase-linear filter 1 0-50 tliktor indiioctaber 1987 i /■ ' a r •wo 1 C«f*7 ceptable number of compo- nents) to simulate any phase behaviour with the aid of a delay circuit. All-pass networks have some in- teresting properties: (a) they cause a phase shift, but no signal attenuation over a given frequency range; (b) the phase shift caused by them is twice as large as that caused by a filter of the same order. From this, it is evident that the low-pass section should be an even-order type, i.e., second-, fourth- or sixth-order. In the present network fourth-order filters are used, since these give a sufficiently steep roll-off and do not unnecessarily com- plicate the circuit. Like all fourth-order networks, the present consists of a cas- cade of two second-order fil- ters. For the present purposes, these should be identical to en- sure that the phase behaviour of the all-pass network will be the same as that of the filter. It was found that the Linkwitz- Riley (Squared Butterworth) filter is eminently suitable for the present network, because it allows a fairly simple all-pass to be designed with only two opamps. The resulting circuit has exactly the same phase behaviour as a fourth-order Lmkwitz low-pass filter. Note that the cross-over frequencies are —6 dB points (as in all Lmkwitz filters), since there is no phase shift between the two channels. The relative ampli- tude vs frequency character- istic is given in Fig. 3, while the three photographs illustrate the typical performance of the net- work. The photographs show the output voltage at the low- and middle-frequency ter- minals (a) slightly below the cross-over point, (b) at the cross-over point, and (c) slightly above the cross-over point. No phase differences between the two signals are discernible anywhere. Circuit description In the circuit diagram of Fig. 4, opamp Ai is used as a buffer between the input signal and the filter proper. If necessary, the input signal may be attenu- ated by Pi; the total amplifi- cation of the network is unity. The low-pass filter is con- structed around A2 and A3, while the associated all-pass filter is based on As and A?. The attenuation due to band-pass filter Ae is compensated by Ai. The low-pass section for the middle frequencies consists of A« and A». Here, two identical all-pass filters are required, and these are formed by At-As in the low section and by A11-A12 in the high section. That com- pletes the low-pass filter. The three outputs of the net- work are taken to preset poten- tiometers that enable matching For the middle-frequency sec- tion, the output signal of As must be subtracted from that of As, which is effected by A 10 . Finally, the output signal of As is subtracted once more from that of A 12 , which is done by An. That completes the high-pass function. Parts list Resistors: Ri;R? = 1 K 5 J R3 to R*. Ris to R17; R23 to Rj*; R11 to Ris = 22K5F Rio to Ru; Rn to R/i; R21 to R30; R34 to R«i = 10KF Pi - 47 KJ cermet preset Pi to P« = 25K J cermet preset Capacitors: Ci ~ 1/iO plastic film C2 to Cs - 22n ceramic Co;C; - 1000/2; 25 V electrolytic C«;C«;C 34 to C<7 = lOOn ceramic C10 to C12 = 10 //; 25 V electrolytic C13 to Cia;C>t;C 2 > = lOn; 2.5% polypropylene Ci«;Czo;Ca to Cj© = InO; 2.5% polypropylene C 31 = 2//2 plastic film C32;C33 = 470n plastic film Miscellaneous: PCB Type 87109 (readers who wish to make their own PCB may order the relevant drawings free of charge on the Order Form on page 691. NOTE: Many components may be available from Audiokits Precision Com- ponents 6 Mill Close Borrowash DERBY DE7 3GU Telephone: <03321 674929 Semiconductors: Di to De - 1N4001 T» = BD139 T2-BD140 ICi =* LM325 IC 2 ;lCa;ICs to ICb = TL072; NE5532; LF353; LM833, OP215 ICb = TL071; NE5534; LF356; 0P27; OP15 each of them to the efficiency of the associated loudspeaker. The quality of the power supply matches that of the cross-over network itself. Circuit 1C i is a voltage regulator, which, in conjunction with two external series transistors, provides sym- metrical output voltages. Diodes Ds and De ensure that the regulator is not damaged at switch-off. elflhtor indi* oclobar 1997 10-51 Construction The network is most con- veniently constructed on the ready-made PCB Type 87109 shown in Fig. 5. The values of the components given in the parts list pertain to cross-over frequencies of 500 Hz and 5,000 Hz. Different frequencies may be calculated with the aid of the Linkwitz formulas in Ref. 4. In several places, capacitors are shown in parallel and resistors in series: this is done to enable the use of as many components of the same value as possible. As usual, the choice of capaci- tors is determined mainly by their loss factor and cost, which normally results in plastic film types. It should be noted that each PCB has its own regulator IC: this is convenient where the network is fitted in the loud- speaker enclosure. The impedance at the network outputs, depending on the pos- ition of the presets, has a maxi- mum value of 12 kilohm. Since this may be on the high side for certain output stages, the value of the presets may be reduced to 5 kilohm, which results in a maximum output impedance of 2.5 kilohm. Where this is done, the value of Cji should be in- creased to 4//7. A useful rule of thumb is that the input im- pedance of the output stage must be at least ten times as large as the output impedance of the network. The PCB may be used to con- struct a two-way network, in which case the following com- ponents are omitted: IC 2 ; ICs; IC6; R? to Ru; R23 to R2$; Rji to R41; C19; C201 C23 to C30; C33; Pi Furthermore, a wire link should be fitted between pin 1 of A 3 and another between pin 7 of A? and Cia References 1. S. Lipshitz & J. Vanderkooy, A Family of Lineal-Phase Cross- over Networks of High Slope Derived by Time Delay (Journal of the Audio Engineering Society, Jan. & Feb. 1983). 2. & Lipshitz and J. Vanderkooy, Is Phase Linearization of Loud- speaker Cross-over Networks Possible by Time Off-set and Equalization? (JAES , Dec. 1984) 3. S. Lipshitz and J. Vanderkooy, Use of Frequency Overlap and Equalization to Produce High- slope Linear-phase Loud- speaker Cross-over Networks, (JAES, March 1985) 4. Linkwitz Filters, Elektor India, May 1987 car headlight alarm This circuit is designed to give an audible and visible warning to the absent-minded motorist who forgets to switch off the headlamps when leaving his car. The power supply to the circuit is taken from the headlamp switch, represented by S2. If the headlamps are switched off then the alarm obviously receives no power and does not operate. The actual light switch in the car will be more complex than S2 since it also controls the sidelights. How- ever, examination of the car wiring diagram and a tittle probing with a multimeter will soon show which terminal of the switch acquires a positive voltage when the head- lamps are switched on. SI represents the car ignition switch As long as the ignition is switched on pins 2 and 6 of IC1 are pulled high via D1 and Rl When the ignition is switched off, however, this voltage will fall as Cl discharges through PI PI sets the time allowed for switching off the headlamps before the alarm sounds When the voltage on Cl falls below the trigger threshold of ICI then, assuming the headlamps are still switched on, the output (pin 3) of ICI will go high, turning on Tl, This lights the seven segment LED display which gives an ‘L’ indication. If the expense of a LED display is not thought to be justified then a single LED or lamp could be used Tl also triggers IC2, which is connected as a monostable multivibrator. The output of 1C2 goes high, thus activating astable multivibrator IC3, which begins to oscillate, producing an alarm signal from the loudspeaker. The length of time for which the alarm sounds is determined by the period of the monostable IC2, which may be adjusted by means of P2. P3 adjusts the volume of the alarm signal. To prevent the possibility of IC2 being spuriously triggered when the headlamps are switched on, T2 is provided. When the headlamp switch is closed C5 begins to charge through R6 and R8, which momen- tarily turns on T2. T2 thus holds the reset input (pin 4) of IC2 low so that it cannot trigger. 10-52 elektor irvdia October 1987 16 KBYTE CMOS RAM FOR C64 by P Verhoosel A non-volatile block of RAM or pseudo-ROM for plugging into the Commodore 64's expansion slot. The expansion port at the rear of the Commodore 64 micro- computer is a 44-pin (22 + 22) female edge connector. The ex- pansion slot— also referred to as bus. cartridge or module port- enables plugging in extension modules that require direct ac- cess to the address bus, data bus, and a number of control lines, of the Type 6510 CPU and its support chips inside the computer. Because of this direct connection, due care should be taken not to damage the system by inappropriate connections, overloads, or short-circuits. The signal func- tions and pin assignment of the expansion port are shown in Table 1 and Fig. 1 respectively. Viewed from’ the computer’s keyboard, and counting from the left to the right, pins 1-22 in- clusive form the upper row, and pins A-Z inclusive the lower row. Notice that letters G, I, 0 and 0 are not used. Connec- tions "GAME and EXROM make it possible to gain external con- trol over the C64’s memory con- figuration, and have special significance for the present memory module. The system configuration At the heart of the C64’s memory decoding circuitry is integrated circuit U 17 , a Pro- grammable Logic Controller (PLA), manufactured specifi- cally for the C64. A total of 16 lines are fe d into t his IC , in- cluding GAME and EXROM, giving 2 ,6 = 65,536 (64 K) poss- ible combinations. The 8 output lines of the PLA connect to internal devices including the BASIC ROM, the SYSTEM ROM, the character generator. CIA1, CIA2, and the RAM. The PLA’s input/output ratio, 256:1, already indicates that a number of input combinations are necessarily duplicate and/or illegal to give a useful configuration of the C64’ memory map, which is shown schematically in Fig. 2. The decimal and hexadecimal address notations are given to the left and the right of the 4 Kbyte memory blocks, re- spectively. When the C64 powers up with the original operation system, the fol- lowing PLA inputs are driven logic high: LORAM, HIRAM. EXROM, GAME, CHAREN. Also shown in Fig. 2 are switches for cont rolling the logic le vel on the GAME and EXROM inp uts of the expansion connnector. EXROM is active in memeory area $8000 - S9FFF (32,768 - 40,959), GAME in the next higher 4 Kbyte block, $A000 - SBFFF (40 ,960 - 4 9,151). The sw itches for EXROM and GAME offer four possible logic configurations: a) GAME = 1; EXROM = 1. b) GAME = 0; EXROM = 1 c) GAME = 1; EXROM = 0 d) GAME = 0; EXROM = 0 Although not harmful to the C64 hardware, combination b pro- duces a hang-up, which can only be ended by altering the switch configuration and reset- ting the computer. Combination a is valid when the computer is powered up, while c can be selected with the aid of switch Sr on the pres- ent board. An additional switch, S 3 , can be closed following S 2 . and enables selecting combi- nation d. Combination b is im- possible to select thanks to the practical switch configuration. Circuit description The circuit diagram of the RAM extension is shown in Fig. 3. When S 3 is opened, the RAM module is switched to the write protect mode, and resistor Ri ensures a fixed level at the WE (write enable) inputs of RAM chips IC3 and IC«, which then behave as ROMs, since they can only be read from, not written to. Gates Ns and Ns-N? combine address fines A13, A14 and A15 into a CS (chip select) line for each of the 8 Kbyte RAMs. Gate Nt plus switches S 2 » and S 3 a en- sure the correct set-up times for read operations in the RAMs. Parallel combination R3-D1 charges the on-board 3.6 V NiCd battery from the com- puter's 5 V supply. When the computer is off, the battery supplies the (very low) data retention current for the CMOS RAM chips. Components C 1 -R 2 -D 2 prevent dips and tran- sients on the RAM supply lines when the computer is switched off, and the battery takes over. It should be noted that a dry bat- tery is preferable over a NiCd cell when the computer is not used for periods longer than alefctor india oaobar 1967 10-53 about a month, because a NiCd cell inevitably loses its charge due to its self discharge cur- rent. R3 is omitted when a dry battery is used. Applications Switched to configuration c. the battery back-up RAM makes it possible to slightly modify the resident BASIC interpreter for individual purposes, copy parts of it into the RAM/ROM mod- ule, develop and store new utilities, or have machine language programs perma- nently available. Memory area 32,768 to 40,959 is covered en- tirely by IC3 , and is fully access- ible to the programmer. Configuration d selects the full 16 KByte RAM block, which then takes the place of the 8 KByte Microsoft BASIC ROM and the internal memory block in this area. When RESET switch Si is pressed, the operating system in the C64 searches for the following tokenized code starting at $8004: S8004 $8005 $8006 $8007 $8008 C3 C2 CD 38 3» Translated into ASCII, this stands for CBM80 if the MSB, D7, is ignored. If this 5-byte string is found (cold boot), the CPU jumps to the address stored in location $8000 (L) and $8001 (H). The 16-bit vector for a warm start is located in the next two higher locations, $8002 and $8003. Construction The compact, ready-made printed circuit board for con- structing the RAM extension is a double-sided, but not through-plated, type, which holds all the components— inclusive of the battery and the switches— and plugs straight into the C64’s expansion slot. The track layouts and compo- nent mounting plan are given in Fig. 4. Commence the construc- tion with fitting the resistors, capacitors, diodes and the wire link. Note that some compo- nents, including the IC sockets, are soldered at both sides of the PCB to effect through-plating. At the copper side, all connec- tions are soldered, at the com- ponent side only those whose solder islands are not covered 10-54 indi» October 1987 C-64 Fig 1. Pin assignment on the expansion port at the rear of the C64 computer. Table 1 Signal functions on the C6 4 expan sion port: Pin Signal Function 1 22 Z GND System ground 2/3 + 5 V IVcc) Power supply for User Port and Cartridge devices (450 mA max.) 4 IRQ Maskable CPU interrupt request line (active low). 5 R/W CPU output line. Memory read: 1; memory write: 0. 6 DOT CLOCK 8.18 MHz dot clock signal from video controller. 7 TToT Active low outputs for memory control. 11 ROML B ROMH 10 1/02 8 GAME Active low inputs for memory control. 9 EXROM 12 BA Bus available signal from the VIC- 11 controller. 13 DMA Direct memory access request line. 14 D7 Unbuffered 6510 databus. 21 DO C RESET Direct CPU reset line for initialising the computer. D NMI Non maskable CPU interrupt line. E : Capacitor: Ci = lOOn Semiconductors: Di;D* - 1N4148 ICi - 74HCT00 IC2 = 74HCT10 ICj;IC 4 = 6264 8K x 8 static CMOS RAM as IC4 A6 A7 RAM as 6264 A9 A10 S A000 All A 12 $ BFFF RESET Miscellaneous: Si= miniature SPST switch. Sj;Sj= miniature DPDT switch. S< - Digitast momentary action key, Electromail stock no. 337-368. PCB mount sealed 3 6 V NiCd battery with solder tags, e g. Mapim order no. RK46A. PCB Type 87082 (available through the Readers services!, RESET N1...N4 = ICI = 74(HCT)00 N5...N7 = IC2 = 74(HCT)10 Fig. 4. The printed circuit board for making the RAM module. selex-27 Time* Lapse Photo graphy If you have seen old silent movies having the stars like Buster Keaton and Charly Chaplin, you must have often wondered how they picturised the funny hectic movements of the these stars. The movie cameras were hand operated in those days and the film making speed could never be maintained steady. When the projector runs at a speed faster than the film making speed, it results into these funny hectic movements. It is exactly the opposite of a film showing a slow motion sequence, where the film making speed has to be much higher than the projection speed An amateur movie camera’ can be easily fitted with a gadget to shoot the fast motion sequences for creating comic effects If the camera has a socket for accepting remote control release cable, you don't even have to open the camera to make any internal connections. In case of a super-8 camera, the film-making speed is maintained constant at 18 frames per second With a simple electronic device described here, it is possible to obtain speeds as low as one frame every four seconds, and a maximum speed of 10 frames per second. When this film is shown with a projector running at normal speed, it results in fast chopped movements of the actors. Circuit: The heart of the circuit is the timer 1C 555 The timer produces short pulses to activate the relay. These pulses are negative going pulses and allow a current to flow through the relay coil whenever they occur. 10-56 etoktor indi* October 1 987 As the other end of the relay coil is at 9V, the relay is energised during the period of the pulse, which is approximately 15mS Such a short duration is selected because we need each pulse just to expose one frame. Potentiometer PI adjusts the time interval between the pulses, which gives a variable film making speed. The relay contacts can be connected to the remote control socket of the camera. A reverse biased diode 01 must be connected across the relay coil to protect the 1C from the peak voltages of the back EMF produced in the relay coil when the current suddenly falls. D1 becomes forward biased during the occurance of these peak voltages developed across the coil and short circuits them, thus preventing these peaks from damaging the 1C The circuit is supplied by a 9V miniature battery. As we have a 6V relay in the circuit, it is quite likely that the batteries may get exhausted quickly. Construction : The first step in construction of this project is obtaining a suitable jack Figure 1 : The time-elapse triggering Circuit enclosed in a standard enclosure. Figure 2 : The 555 1C timer module is the heart of the circuit. selex which correctly fits into the Remote socket of the camera. Mostly the 2.5mm or 3.5mm jack plugs may be suitable. The relay should preferably be a PCB mounting type relay The coil resistance must be at least 450, because, a lower resistance may overload the 1C output. The 1C socket is soldered first, then the jumper wire connections. R1, R2, Cl D1 are soldered next, and finally the relay. The component layout is shown in figure 4. The polarity of diode and orientation of 1C pin No. 1 must be carefully maintained. The cathode of the diode points towards may have to be changed depending on the type of relay being used. Potentiometer PI and switch SI and the battery are fitted in the enclosure and connected to the PCB through flexible leads. Only two wires go from the PCB to the potentiometer. Two terminals of the potentiometer are soldered by a jumper wire to each other as shown in figure 5. If the 4.7 M 0 potentiometer is not available, one can use two 2.2 M 0 potentioneters and connect them in series. The 1C 555 must be inserted into the socket correctly. The pins may have to be bent inwards slightly if the 1C is new. The marking notch is towards the relay. The circuit has been designed around the ordinary 555 1C and CMOS version of the 1C should not be used. After completing the soldering and connections, the operation can be easily checked without connecting the circuit to the camera. Connect the battery and switch on SI. Be careful about the battery polarity, otherwise the 1C and diode is most likely to be damaged. On switching SI on, the relay should start making a ticking sound. The rate of ticking must change when PI is moved. If there is no ticking sound from the relay, check the connections once again. Now the circuit can be tried out on the camera. Do not load the film into the camera during the first trials. When you are sure that the circuit works properly, you can load the film and start shootingl In case of cameras which require longer start up periods, value of Cl must be increased. For those readers who do not have access to an amateur movie camera for this project, the circuit will still prove useful as a reference. Additional information on the timer 1C 555 is included here for the same purpose. Timer 1C 555 555 is a universal timer 1C. Figure 6 shows the internal block diagram enclosed inside the dotted lines. Also 4 Component List : R1 = 47K11 R2 = 22KI1 PI = 4.7 Mil (Log.) Cl = luF (Foil type) D1 = 1N4148 ICI = 555 Re = 6V/4511 Relay with 1 N/O contact. Other parts : 1 9V Battery 1 Battery Clip 1 SELEX PCB (40 x 100 mm) 1 8 Pin DIP Socket 1 Suitable casing 1 Knob for potentiometer 1 Suitable jack for connecting to camera socket. 1 Toggle Switch. Figure 3 . Besides battery. Potentiometer and the ON/OFF toggle switch, all other components can be fitted on to one small SELEX PCB of 40 x 100 mm. Figure 4 : Component layout of the circuit. Attention must be paid to correct polarities and 1C orientation. elefctor mdia October 1987 1 0“57 selex Figure 5 : Potentiometer with two terminals directly shorted to each other. Figure 6 : The internal circuit block diagram of 1C 565. The I capacitor Cl alternately charges and discharges. 6 9 V shown for convenience are the main components in the time-lapse circuit. When the power is applied to the circuit, the capacitor Cl starts changing through R1, R2 and PI Adjusting PI modifies the changing current of the capacitor Cl and thus decides the time taken by it to reach full charge. The smaller the value of PI, the faster is the charging. The rise in voltage across Cl is monitored by the two comparators inside the 1C. The capacitor voltage is continuously compared with 2/3 and 1/3 of the supply voltage. The reference voltages of 1 /3 and 2/3 values are obtained from the supply voltage by the potential divider chain having three equal resistances. As soon as the capacitor voltage exceeds the value I 2/3 Ub, comparator 1 is activated This sets the flip flop and turns the transistor T1 on. This provides a path for discharging the capacitor Cl through R2 and T1 . When the falling voltage on Cl goes below 1/3 Ub, the comparator 2 is activated and resets the flip flop. As the voltage on base of T1 becomes 0, it is turned off, cutting open the discharging path for Cl. It starts charging again through R1, R2 and PI until, of course, tfie voltage on Cl reaches 2/3 Ub again. Then the cycle repeats The flipflop output also drives an inverter at the output of the 555 and gives the output voltage on pin 3. The output at pin 3 thus switches between OV and GV. The photograph of the CRT screen of an oscilloscope is shown in figure 9 to indicate how the charging and discharging cycles take place. The top curve is the voltage on the capacitor Cl at pin 2 and the lower curve is the voltage on pin 7, that is the collector of T1 The charging period depends on R1, R2 and PI Discharging depends only on R2 as R1 & R2 are fixed values, discharging period is fixed — which corresponds to the pulse width PI controls the charging period, and in turn, the time interval between two pulses. Figure 7 : The charging cycle Figure 8 : The discharging cycle Figure 9 : Waveforms of the capacitor voltage and transistor collector voltage 10-58 elektor rntha October 1 987 selex Universal Power Supply A good variable power supply is a basic requirement of every hobby aboratory. It is true that many interesting SELEX circuits can be supplied from dry cells, however, considering the rising cost of these cells, one would rather go in for a good variable power supply. Compare the cost of one Kilowatt Hour power drawn from the mains supply and that of the same power supplied by dry cells and you will immediately realise the importance of having a variable power supply of your own. The SELEX Universal Power Supply described here, satisfies these requirements. It has two output ranges, one from 2.7 V to 1 2 V and the other from 10 V to 24 V. The output is short circuit protected. Current limiting is adjustable These two features are mainly incorporated for preventing accidental damages to the power supply as well as your circuits. The Circuit The most important part of the power supply is the integrated voltage regulator L 200, It looks similar to a power transistor-with five terminalsl The number of terminals obviously means that there is much more in it. A simplified block diagram of L 200 is shown in figure 1. The regulator is internally protected against electrical and thermal overloads. It is not affected by a short circuit at the output, or by insufficient cooling. The voltage regulation takes place as long as it is ensured that the control input (Pin 4) gets 2.7V. The current limiting sets in when the voltaged between the output (Pin 5) and the current limiting input (Pin 2) exceeds the value of 0.45 Volts. These are inherent electrical properties of the L200 and cannot be altered. The output voltage has been divided in two ranges, to avoid heay lossess and overheating at low voltages. If suppose the input voltage is 28V and we need an output voltage of 5V, then somehow the regulator must ' destroy" these extra 23 volts. This will result in loss of power as well as overheating. If we have an input of 14V and the output of 5V, then the regulator has to reduce the input only by 9V By dividing the output into two different ranges the efficiency has been increased and heating is reduced. The switching over from one range to another is done by switch S2 (figure 4). The effective connection changes inside the circuit are shown in figure 2 and 3. In the lower range both the transformer windings are connected in parallel and diodes D1 and D3 are in the rectifying circuit. In the higher range the windings are in series and the bridge made of 01. D2, D3, D4 comes into the rectifying circuit, thus doubling the rectified voltage which is fed to the regulator. «l«*tlor ir>dia October 1 987 10-59 selex The remaining part of the circuit shown in figure 4 serves to adjust the output voltage (PI, R4 .... R9), set the current limiting (P2, T3 etc.) and to give the indication of operation (T1, T2, and the LED D5) This is how the adjustment of the output voltage takes place: PI and the resistors R4 R9 form a voltage divider network. The junction of R4 and R6 or R8 and R6 (depending on the range) is connected to the control input of the regulator. The regulator adjusts the output voltage in such a way that voltage at the control input remains constant at 2.7 V. The output voltage thus depends upon the setting of potentiometer PI. The setting of current limiting is somewhat difficult to understand. It becomes effective when voltage difference between pin 2 and 5 of the regulator increases beyond 0.45V. The voltage present here is equal to the voltage drop over R12 plus the voltage at the sliding contact of potentiometer P2. The constant current source formed using T3 provides for the fact that the value of output voltage does not affect the current limiting function. As the voltage drop across R12 depends upon the current drawn by 0 mut Input the load and the voltage at pin 2 is derived from a constant current source, the setting of current limiting is independent of the voltage at the output. The green LED D8 has a dual function. It serves for switching control as well as for controlling the constant current source T3. Transistors T1 , T2 and the Red LED D5 are used for fault indication, when output current reaches the limit value that is set for it. In normal condition the voltage on pin 4 is 2.7 V, which is greater than the threshold voltage of D6, D7 and base emitter junction of T2. Thus T2 is always conducting. This causes the base of T1 to remain at zero volts and it is always OFF. LED D5 also remains off. But as soon as the voltage on pin 4 reaches about 2V, which is less than the required voltage to keep T2 ON. T2 is turned off and T1 then starts conducting. Red LED D5 glows, indicating a fault condition Diodes DIO and D1 1 serve as the protection for the circuit. Figure 1 : Voltage regulator 1C L200 is the heart of the SELEX- Universal Power Supply. The functions of voltage regulation are also supplemented by protective functions. Figure 2: The output voltage is divided in two ranges. In case of low range, the two transformer windings are connected in parallel. Figure 3: In the higher voltage range, ge, the transformer windings are connected in series. The rectifier in this case is a bridge rectifier. 10-60 •lefctor india October 1 987 Construction : SELEX PCB of size 2 80x100 mm) is required for constructing the component layout of the circuit on the SELEX PCB '■Cl is the voltage regulator L 200. Conductive paste must be used while mounting the device on the heatsink. It can be mounted on the back panel of the enclosure, and the heatsink can be fitted onto the back panel in such a way that effective cooling takes place It should be ensured that only thermal conduction takes place, and not electrical, because the cooling fin of the 1C is also connected to the earthing pin No other pin of the 1C should ever come in contact with the earthing pin. Cross section of all conductors which carry the load currents must be at leat 1 mm 2 . The length of these conductors must be kept as small as possible. The same is true for the leads coming from the transformer. The transformer the fuse and the two-pole switch must be placed in such a manner, that the other components of the circuit do not come in Figure 4: The circuit of the universal power supply is somewhat complex compared to usual SELEX circuits. The cost also is somewhat higher, but it is worth that much of expenditure, considering the advantage and safety it provides. Figure 5: Component layout of the circuit on a SELEX PCB of stxa 2 (80 x 100mm). If you follow this layout accurately, nothing can go wrong, in spite of the complex circuit. IC1 must be connected thermally to a heatsink. Component List: R1 = 15 Kll R2 ' 6801! R3 = 15011 R4 = 1.2K11 R5. R7. R1 3 = 22011 R6 = 2.2KO R8 = 2.7 Kll R9 = 330 RIO = 68011 R11 = 18011 R12 0.4711. 1W PI = 4.7K11 Linear P2 = 47011 Linear Cl = 2200 uF/25V Electrolytic C2 = 2200 UF/40V Electrolytic C3 = 220 nF C4 - 1 uF/35V Tantalium T1. T2. T3 = BC 547B D1. 02, D3.D4 ' IN 5404 D5 = Red LED 06, D7, D9 - IN 4148 D8 - Green LED DIO. Dll = IN 4001 IC1 = L200 Other parts : Transformer - 12-0-12V/1.2A 51 = DPST Mains Switch 52 = SPDT Switch. 2A rating. Heatsink for IC1 Si = 250mA fuse, with holder 1 SELEX PCB. Size 2 (80 x 1 00mm) elektor mdia octobe* 1987 10-6 ■ Voltage between Base of T3 and earth : 3V DC ■ Voltage between emitter of T3 and earth : 2.5V DC Independent of potentiometer setting ■ Voltage over D9 approximately 0.8 V DC. Any wrong readings during the test procedure indicate that the particular component is either connected wrongly or is defective. regulator part of the circuit from the rectifier Both the LEDs will now glow, when the power is switched on. The following values should be measured : ■ Voltage at each transformer winding : 1 2 V AC ■ Voltage over both windings together : 24 V AC ■ Voltage over Cl (Point B to earth) : 18V DC ■ Voltage over C2 (Point A to earth) : 36 V DC ■ Voltage over both LEDs ; 2 V If all these values are correct, it means that the transformer and rectifier part of the circuit is correct contact with the mains supply A voltmeter and an ammeter can be used for indicating the output voltage and load current, depending on the budget. Both can be measured with a multimeter and the knobs of patentiometers PI and P2 can be fitted with calibrated scales on the front panel LEDs are fitted with two standard LED holder sockets on the front panel. The enclosure should be of sheet metal, so that cooling can be more efficient. The minus pole of the power supply should not have any connection with the enclosure body. It is necessary to have the potentiometers and resistors of good quality to achieve the expected performance. As tne next step, connection between P2 and R13 is desoldered. Now if a multimeter set to 100 mA range is inserted between point B and the collector of T3, it should indicate a current of 1 3 mA approximately. The unsoldered connections can now be restored, and following voltages should be measured. ■ Voltage between Pin 4 of IC1 and the earth: 2.7V DC, independant of the potentiometer setting. Reduces only when current limiting sets in. ■ Voltage between D6 and D7 : 1.2V DC Testing the power supply If alt the components have been soldered correctly as per the component layout the circuit must function correctly after it is switched on. Both the voltage ranges can be confirmed with a multimeter. Whenever the regulator switches off due to overload, the power supply from mains must be switched off for some time and then restarted. If the circuit does not function as expected, it can be tested stage by stage with a multimeter. First of all the component layout and interconnections must be checked The diode and capacitor polarities must be correct Pin orientation of the 1C and transistors must be carefully checked. It must also be ensured that the cooling fin of the 1C is not shoit circuited with any other pin or with any other component It must be connected only to the minus pole of the power supply. Before starting further measurement on the circuit, point C must be disconnected from the pole of switch S2a. By doing this, we have isolated the 10-62 el«fctor mdia October 1987 £W PRODUCTS • NEW PRODUCTS • NEW useful to designers (manufacturers) of dedicated type of instruments based on 8748, 8749, 8035 and 8039 single chip microcomputers that contribute to low cost and compactness of the final equipment. Model RC 8749 incorporates features like extremely flexible break point and debug facilities; program may be single stepped or run in full (11 MHz) realtime, setting of any number of break points or triggering by either program or external RAM Accesses; Auto Step, Auto Break, triggering of oscilloscope or logic analyser during break points; live display and keyboard while running in any mode; suspension or termination of execution by command etc. For further information please contact: STATIC SYSTEMS Wza- 1 16, Ramdatt Enclave Uttam Nagar, New Delhi 59. Phone No: 553862. For further details please contact: SR EE RAM ENGINEERING ENTERPRISES 8 Udyog Bhavan, Butsroyce Lane, Vakola Bridge Santacruz (East) Bombay 400 055 Telephone No. : 612 58 77. EPROM PROGRAMMER The model 2001 Intelligent Eprom Programer is manufactured by Jumbo Electronics. It supports 27 series Eproms upto 27256 and also 8748, 8755 and 8751 Microcontrollers and has fast programme mode, key selectable programming voltages. Two RS232-C channels for remote mode and host communication for down load/up load in intel hex format and powerful editing features. It is compact and lightweight suitable for lab as well as field applications and available in plastic cabinet. METAL OXIDE VARISTORS (MOVs) Metal Oxide Varistors are transient voltage suppressors and find extensive applications as protective devices. These devices are capable of suppressing high voltage 'spikes' and surges appearing on AC/DC lines, to acceptable levels, thus protecting electronic components and systems from failures. MOVs are recommended for use in Thyristor Control Systems, SMPS, Voltage Stabilisers, COLORCARE COLORCARE is a protection unit for Color T.V., VCR, Electronic Typewriter, Photostate machine and Computers. It is reported to protect the equipment from Surges, Broken power supply, over voltage and under voltage. PLCs, Electronic Timers, Computer Systems, Television and VCRs, Hi Fi Systems, Relay Contact Protection, motor protection and a wide range of other equipments. MOVs of internationally acceptable quality have been developed by Elpro International Ltd. an affiliate company of General Electric Co., USA. Devices are now available locally in a wide range of operating voltages from 110V to 510V and for various energy ratings. For further information please contact: JUMBO ELECTRONICS Unit No. 20, Ghanshyam Indl. Estate, Veera Desai Road Andheri West) Bombay 400 058 Phone No: 623586, 574980. For further information please contact: TRANSWORLD ELECTRONICS Marketing Division 26/571, Oottukuzhy Trivandrum 695 001. For further details contact: RC INFORMATION TECHNOLOG Y SYSTEMS PVT. Ltd. 14 13 Dalamal Tower Nariman Point Bombay 400 021 HARDWARE Sree Ram Engineering Enterprises specialise in fabrication jobs in C.R.C.A. and Aluminium. They undertake to manufacture Chassis, Covers, Doors & Panels for Computer Peripherals, Telephone Meter & Power Supply Boxes etc. Custom fabrication jobs as per samples or drawing are also executed. TRACK CONVERTER Static Systems have introduced a new product for use with computer disk drives. It allows 40-Track software to be run on an 80 Track Drive. The 80/40-Track converter is a plug-in unit. It comes with a 34-pin cable and connector for instant installation. No soldering is required. TEMP. INDICATOR The NAINA NT 503 Digital Temperature Indicator has been designed for laboratory use. Based on LSI/MOS Devices this instrument is available in ranges of 0-100°C/-50°C to +200° C/0 to 600° C/0 to 1 200° C with suitable PT 100, Thermocouples or semiconductor probes. A variety of sensors is available. For further information please contact: NAINA ELECTRONICS PVT. LTD. 181 fi. Industrial Area Chandigarh. For further information please contact: I.G.E. (INDIA) LTD. "Nlrmal", Nariman Point Bombay 400 021. EMULATOR FOR 8748 FAMILY RC-8749 is an indigenously developed real speed Emulator 10-64 elsktor mdie October 1 987 ;w PRODUCTS • NEW PRODUCTS • NE Ashin guarantees high quality and long durability for all models. As a specialized manufacturer for drums, Ashin undertakes development of new drums also as per customers specifications. The prices for Ashin Drums are very reasonable, which should be very attractive to PPC Manufacturers. Samples and prototype quantities are available from Stock, larger quantitites 4 to 8 weeks. 100 pc. price for military temperature range version, $16.17 ea. For further information please contact: NILKAMAL CRATES & CONTAINERS 5 Rena Chambers, First Floor New Marine Lines Bombay 400 020. INSULATION RESISTANCE TESTER MECOMEG Brand Insulation tester is available housed in unbreakable ABS housing with Acrylic front cover. The instrument is a transistorised, battery operated type with exclusive features such as single person operation, push button control. It is supplied complete with carrying case and testing leads. Various models are available with Voltage ranging from 100V to 1000V and resistance ranging from 0-20 Meg Ohms to 0-500 Meg Ohms depending upon requirements MARKEM 525 HAND ACTUATED ROTARY OFFSET PRINTER This is a hand actuated offset printing machine. This is suitable to enhance print quality and productivity on small production runs. This system provides superior print qualities in the rotary offset process for brighter and sharper printing. This machine is suitable for small lots of products— DIP8s, TO-220's, flat packs, chip carriers and general products with at least one flat side. Although cycle speed and through-put are dependent on the operator, production rates of 800—1500 units per hour are attainable. Specifications: Print area: 7/8" x 1" (22.2mm x 25.4mm). Max. part thickness: Variable Cycle rate: 800-1 500 cycles/ hour. Mount: Bench. Weight: 30 lb (13.65 kg). For further information please contact: SARAS ELECTRONICS Suite 301, Purohit House 144 Mint Street Madras 600 079 Phone: 1044) 32497 Cable: 'SARAS INDIA' Madras 600 079. For further information please contact: HI TECH RESISTORS PVT. LTD. 1003/04, Maker Chamber V Nariman Point Bombay 400 02 1. PCB ACCESSORIES PCB manufacturers in the country can avail of this system for stacking storing and transporting PCBs. Called 'PCB Carrier', the system is manufactured by Nilkamal Crates and Containers. The PCB Carrier consists of grooved plastic panels held firmly by aluminium strips and removable stoppers which plug unused grooves, thus preventing damage. The Carrier can be adjusted, with a simple screwdriver, to tit almost any size of PCB. It is presently available in 4 models in normal & anti-static variety. In the same line the company will shortly introduce a 'PCB Holder' which is a table-top unit for storing PCBs on the assembly line. POWER MOSFET Supertex has announced the latest in a series of surface-mount power MOSFET Quad Arrays. The VQ3001 NF is offered in a 20-Terminal, ceramic surface-mount leadless chip carrier, previously used exclusively for ICs. The New Quad Array two pairs of completely independent N and P channel MOSFETs in this surface-mount package. The NF package is designed for use in both Industrial and High-Reliability /Military (MIL-STD-883C) applications including motor controllers, amplifiers and drivers for relays, hammers, solenoids, memories and displays. Th»-VQ3001 N F offers a BVqSS °f 40V. Max Rqs (ON) is 3 ohms for each N + P channel pair. For further information contact: MECO INSTRUMENTS PVT. LTD. Bharat Industrial Estate T.J.Road, Senree Bombay 400 015. PHOTOCONDUCTOR DRUMS (SELENIUM DRUMS) Ashin Electric Mfg. Co., Ltd. Korea offers Selenium Drums in over 40 models. These drums are suitable for use in Plain Paper Copiers such as Sanyo, Apeco, Toshiba, Ubix, Royal, Konishiroku, Fotorex, Panasonic, A.B. Dick, Copier Selex, Cybernet, Minolta, Saxon, Nashua, Ricoh, Mita, Gestetner, Develop, Utoax, Adler, Rex Rotary, Kardex, Infotek, Savin and many others. For further information please contact: M/s. KELLY CORPORATION 14 13, Dalamal Toner Nariman Point Bombay 400 021. Telephone No: 244286. Telex: 1 1-5858 KELY IN. 10-66 elefclor mdia October 1 987 W PRODUCTS • NEW PRODUCTS • TAMAYA DIGITIZING AREA LINE METER Planix 5000 Area Line Meter Works on a totally new concept developed through unconventional approach leading to unsurpassed performance standards. The rotary encoder and the state-of-art electronics makes Planix 5000, easiest, fastest area Line Meter. This Meter allows you to measure area and the length of the line. The standard lines are easily measured by simply setting the trace point at each intersection of the figure and the rest is done by the built- in computer with a resolution of 0.05 mm; length of curve line needs to be traced, for measuring. Planix 5000 is a TOTAL STATION for the draftsman. In addition to its own microprocessor, PLANIX 5000 will interface with the large computer or other RS-232C compatible units. PLANIX 5000 is a compact cordless instrument operating on NiCd Batteries and comes in a carrying case. For Further details please contact: TOSHNI-TEK INTERNATIONAL 267 KUpauk Garden Road Madras 600 010 SPIKEBUSTER MAGNUM ELECTRIC COMPANY PVT. LTD. has introduced a voltage spike and noise suppression outlet strip called SPIKEBUSTER. It consists of an EMI/RFI filter and a voltage spike protection circuit built into a power strip with three 5 Amp sockets and a control switch. By plugging SPIKEBUSTER into the electricity mains and your sensitive electronic equipment into SPIKEBUSTER, electrical noise and voltage spikes are totally prevented from reaching the equipment and damaging it or causing it to malfunction. Uses are for colour TV sets, VCRs, computers, computer peripherals, medical equipment, electronic instruments, communication systems and other device containing sensitive integrated circuits. The company specialises in power protection equipment and will soon be coming out with a lowpriced standby battery back-up system aimed at the desktop computer market. For further information write to: MAGNUM ELECTRIC COMPANY PVT. LTD' 2 Ramavaram Road Manapakkam Madras 600 089 THICKNESS GAUGE General Tools offer a coating Thickness Gauge. For measurement of a non- magnetic coating on a Magnetic metal. Application Measurement of following nonmagnetic coatings on magnetic metals. 1) Plating— Gold, Copper, Zinc Tin Chromium, Lead etc. 2) Coating— Paint, Resinous coating, Metallic Coating. ' be measured when placed on ! steel base metal. For further details contact: THE GENERAL TOOLS CO. 7, Daulat Mansion Barrack Road, Behind Metro Cinema, Bombay 400 020 BARREL PUMP (HAND OPERATED) FOR CHEMICALS & OILS A hand pump, in all plastic construction, namely Polypropylene (PP) and Thermoplastic Polyester (PBT), is introduced for the first time in India. It is ideally suitable for transfer of chemicals and oils from barrels, carbouys, jerry cans, jars etc. The pump in PP is used for transfer of Acids like Hydrochloric, Sulphuric (Upto 80%) Nitric (Upto 70%), Phosphoric, Acetic, Chromic, Spent Acids etc. It is also used for Inorganic Salt Solutions, Hypochlorite and for Vegetable and Mineral Oils and certain Organic Amines. Hexane, Liquid Paraffin and other Acetates, Plastcisers, Chlorinated Solvents, Polyols, Isocyanates etc. In general these pumps are ideally suitable for transfer of liquid chemicals and oils from barrels and carbouys. They offer suction lift of 3 mts, discharge heads of 15mts and capacity of 30 Ipm. They are extensively used at industries like chemicals, textile processing, pharmaceuticals, pesticides formulation, electronics, PCB Mnfg., sugar mills, dye stuff mnfg., etching plants, degreasing plants, research labs., offset presses, installation where oils, kerosene, diesel are used, and all other places where chemicals and oils are handled. For further information please contact: CHEMINEERS 6 Jagnath Plot Rajkot 360 001 Gujarat State, India. 3) Lining— Resin, Rubber, Paper or any other films of non-magnetic material can The pump in PBT is used for all types of Aldehydes, Ketones, Glycols, Alcohols, Petroleum products and Oils, Acetone and Aniline and their derivatives. Benzene, Toluene, Xylene and their compounds, liquid perfumery products and pesticides, DDB, LAB, Classified ads advertisers index 8085 MICROPROCESSOR TRAINER butlt in EPROM programmer, power supply. 2K CMOS/RAM with dry cell back up expandable to 8 K. 1 2 K user EPROM installed Rs 2975/ All inclusive EPROM Eraser Rs 500/ Contact NEW AGE ELECTRONICS, 9 Laxmi Mahal, Near Vandana Cinema. Op- posite Bhatia Compound. Bombay Agra Road, Thane - 400 602 MAKE YOURSELF PRINTED CIRCUITS easily, cheaply and quickly inless than 1/4th the market price. Send Rs 10/- advance, balance Rs 10/- by V P P For constructional details. ARUN ELECTRONICS, 1. Hidayatpur Road, Majhouh. PATNA 803 202 Headphone amplifier Annual 87 September p. 9-45 The Parts list should be amended as follows: R6-2R7. Synthesizer for SW receiver Annual '87 September p. 9-91 The mixer referred to in the 5th line of the text is not described in the Sup- plement of constructional projects, but forms part of a Front end for 5kV receiver, a project that will be included in 303 Circuits, a forthcoming book from Elektor Electronics. Synchronized Slide Changer Annual '87 September p. 9-109 The circuit diagram given below is left out in the article Avoid Delay Get your Printed Circuit Boards designed and made from SHIV ENTERPRISES. P Bhagat Marg, Tuka- ram Nagar. Dombivali (E) - 421 201 ABC ELECTRONICS 10.11 ABR ELECTRONICS 10-16 ADVANCED VIDEO LAB 10-14 AIR INDIA 10-69 APEX ELECTRONICS 10-16 CHAMPION ELECTRONICS 10-63 COMTECH 10-10 COSMIC 10-8 4 CTR 10-13 CYCLO COMPUTERS 10-T2 DYNALOG MICRO 10-65 DYNATRON ELECTRONICS 10-10, 10-14, 10-74 ECONOMY ELECTRONICS 10-04 EXCEL 10-08 GALA ELECTRONICS 10-02 GENERAL ELECTRONICS 10-15 G.S. ELECTRONICS 10-08 HYDERABAD CONNECTRONICS 10-67 IEAP 10-16 INTEGRATED ELECTRONICS CO 10-06 JR COMPUTER BOOK 10-72 JR COMPUTER KIT 10-72 KIRLOSKAR ELECTRODYNE 10-17 LEADER ELECTRONICS 10-74 LEM CO 10-06 LOGIC PROBE IQ-16 MECO INSTRUMENTS 10-77 MOTWANE 10-09 NCS 10-10 PECTRON 10-74 PIONEER ELECTRONICS 10-14 PLASTART ELECTRONICS 10-04 PRECIOUS KITS 10-03 PRECIOUS BOOKS 10-79 MOTWANE 10-09 MECO INSTRUMENTS 10-77 SIEMENS 10-73 SWASTIK 10-70 TANTIA ELECTRONICS 10-06 TEXONIC INSTRUMENTS 10-12 TRIMURTI ELECTRONICS 10-14 UNLIMITED 10-12 VASAVI ELECTRONICS 10-04 VISHA 10 83 VIKAS HYBRIDS 10-08 CORRECTIONS Toilet pointer Annual ’87 September p. 9-49 The 6th line of the text should read pro- posed toilet pointer may be use - Printed Resistors July 1987 p. 7.31 The unit of resistivity is Qmrr^/m, not Q/mm'/m. Computerscope October 1986 p. 10-20 Contrary to the correction given in the June 1987 issue, Cis is a lOOp capacitor. 12V A1.A2 = IC1 = 3240 Re 1 - 12 V. max. 80 mA 10-80 •Wrtor mdia ociobar 1 967 R N No 39881/83 Allowed to Post without prepayment UC No 91 MH BY WEST 228 LIC No 91 Cosmic Nakamichi AX-1000 It's pure black magic sophisticated circuitry, with such powerful Ampli-Cassettc Deck has Vibrating with 250 watts of sonic purity and clarity, that one hears arrived, to cast a spell even on the peak energy, breaking all sound not the reproduction of music but the perfectionist. fri ce R- s 4.500/- all inclusive barriers, touching rare heights,* here actual recreation of it. So get ready for some hypnotism. (only for Bombay city) ccjsmic We are sound Featuring SMPS, a unique advance in audio technology, coining to India fnr thp fir*. I timp. comes, at last an Ampli Deck marvel which will fill your senses as never never before. This classic black model — Makamichi AX- 1 000 with its unique Switch Mode Power Supply (5.M.P.S.) has music surqinq through its Backed by the audio expertise of Cosmic, this latest generation model, has a dynamic one touch recording system, a super hard pent) alloy head, soft touch controls, L E D. peak level indicators, double gap erase head plus much much more for over all excellent performance. This Printer Publisher — C.R. Chandarana, 2, Koumari, 14th A Road. Khar. Bombay 400 052. Printed at Trupti Offset, 103 Vasan Udvog Bhavan, Tutsi Pipe Road. Lower Parcl, Bombay 400 013. Impl®ment.CTV'10