< ■ r ' 49 May 1979 U.K.55p. U.S.A I Can. $1.75 up/te-date elep'tponics for lab and leisure V ”■ programmable timer/controller basic microcomputer Australia S1.50* Denmark Kr. 10 Austria S. 33 France F. 8 Belgium F. 59 Germany DM. 4.20 * recommended Netherlands DFL. 3.50 New Zealand S 1.50 Norway Kr. 10 Sweden Kr. 14 Switzerland F 4.40 advertisement elektor may 1979— UK3 The professional scopes you’ve always needed. When it comes to oscilloscopes, you'll have to go a long way to equal the reliability and performance of Calscope. Calscope set new standards in their products, as you'll discover when you compare specification and price against the competition. The Calscope Super 1 0, dual trace 1 0 MHz has probably the highest standard anywhere for a low cost general purpose oscilloscope. A 3% accuracy is obtained by the use of stabilised power supplies which cope with mains fluctuations. The price £219 plus VAT The Super 6 is a portable 6MHz single beam model with easy to use controls and has a time base range of Ips to 1 0Oms/cm with 1 0mV sensitivity Price £ 1 62 plus VAT. CALSCOPE DISTRIBUTED BY Marshalls Electronic Components, Watford Electronics, Kingsgate House. Kingsgate Place, London. N.W.6. Audio Electronics. 301 Edgware Road. London W.2. Tel: 01-724 3564 Access and Barclay card facilities Tel: 0702 715 155 (Personal Shoppers) 33-35 Cardiff Road. Watford. Herts. Tel: 0923 40588 Maplin Electronics Supplies Ltd. P.0 Box 3 Rayleigh. Essex. 10 £219.00 plus VAT CALSCOPE MODEL 756 FULL ASCII KEYBOARD LOW COST! Fully Assembled Intended for professional micro- processor applications. This one Keyboard will meet most present and future requirements. Full 128 character ASCII 8-bit code Tri-mode MOS encoding. Applications notes for auto repeat, numeric pad, serial output. Upper and lower case characters generated by keyboard with latching shift-lock. Selectable polarity. Site 305 X 14Q X 32mm <12% X 5v. X 1 % in) MQS/DTL/TTL compatible outputs. New guaranteed OEM grade com - ponents. Needs +5 and —12V supply Carter Associates P 0 Box 1 1 262 VIAEBERG South Africa postal code 8018 For non UK orders Price includes air parcel delivery any- where in the world. Most currencies acceptable at exchange rates ruling i— on date your order is posted. Drafts » and cheques acceptable (if personal L Board has space for small low-cost DC/DC o verter so that entire unit operates off single Alpha lock . Extra loose keys available. Supplied complete with full technical data. Rugged mil. spec. G-10 PCB with plated through holes. 2-key roll-over DC level and pulse strobe signal for easy interface to any 8-bit input port microprocessor system video display or terminal board. Strobe pulse width 1 ms. User selection of positive or negative logic data and strobe output. Barclaycard and i cards honoured UK 4 — elektor may 1979 elektor 49 decoder Volume 5 Number 5 other countries surface mail airmail £ 8.50 £ 14.00 I. Subscriptions from other countries surface mail airmail £ 4.85 £ 8.00 Elektor Publishers Ltd., Elektor House, 10 Longport, Canterbury CT1 1PE, Kent, U.K. Tel.: Canterbury 102271 54430. Telex: 965504. Office hours: 8.30 - 12.45 and 13.30 • 16.45. Bank: 1. Midland Bank Ltd., Canterbury, A/C no. 11014587 Sorting code 40-16-11, Giro no. 315.42.54 2. U.S.A. only: Bank of America, c/o World Way Postal Center, P.O. Box 80689, Los Angeles, CA 90080, A/C no. 12350-04207. 3. Canada only: The Royal Bank of Canada, c/o Lockbox 1969, Postal Station A, Toronto, Ontario, M5W 1W9. A/C no. 16^269-7. Please make all cheques payable to Elektor Publishers Ltd. at above address. Elektor is published monthly. Number 51/52 (July/August) is a double issue. SUBSCRIPTIONS: Mrs. S. Barber Subscription 1979, January to December U.K. U.S.A./Can. surface mail airmail £8.50 $21.00 $31.00 Subscriptions normally run to December i June issue: U.S.A./Can. surface mail airmail £4.85 $12.00 $18.00 Back issues are available at original cover price. Change of address: Please allow at least six weeks for change of address. Include your old address, enclosing, if possible, an address label from a ADVERTISING MANAGER: N.M. Willis National advertising rates for the Engl'sh-language edition of Elektor and international rates for advertising in the Dutch, French and German issues are available on request. EDITOR U.K. EDITORIAL STAFF W. van der Horst I- Meiklejohn TECHNICAL EDITORIAL STAFF J. Barendrecht A. Nachtmann G.H.K. Dam J- Oudelaar P. Holmes A.C. Pauptit E. Krempel sauer K.S.M. Walraven G. Nachbar P- de Winter Technical telephone query service, Mondays only, 13.30 - 16.45. For written queries, letters should be addressed to dept. TQ. Please enclose a stamped, addressed envelope or a self-addressed envelope plus an IRC. ART EDITOR: F. v. Rooij Letters should be addressed to the department concerned: TQ = Technical Queries ADV = Advertisements ED * Editorial (articles sub- ADM = Administration mitted for publications etc.) EPS = Elektor printed circuit SUB = Subscriptions board service The circuits published are for domestic use only. The submission of designs or articles to Elektor implies permission to the publishers to alter and translate the text and design, and to use the contents in other Elektor publications and activities. The publishers cannot guarantee to return any material submitted to them. All drawings, photographs, printed circuit boards and articles published in Elektor are copyright and may not be reproduced or imitated in whole or part without prior written permission of the publishers. Patent protection may exist in respect of circuits, devices etc. described in this magazine. The publishers do not accept responsibility for failing to patent or other protection. Dutch edition: Elektuur B.V., Postbus 75, 6190 AB Beek (L), the Netherlands. German edition: Elektor Verlag GmbH, 5133 Gangelt, W-Germany French edition: Elektor Sari. Le Doulieu. 59940 Estaires. France. Distribution in U.K.: Seymour Press Ltd., 334 Brixton Road, London SW9 7 AG. Distribution in CANADA: Fordon and Gotch (Can.) Ltd., 55 York Street, Toronto. Ontario M5J 1S4. Copyright ©1979 Elektor publishers Ltd. - Canterbury. Printed in the UK. What is a TUN? What is 10 n? What is the EPS service? What is the TQ service? What is a missing link? Semiconductor types Very often, a large number of equivalent semiconductors exist with different type numbers. For this reason, 'abbreviated' type numbers are used in Elektor wherever possible: • '741 ' stand for pA741 . LM741 , MC641 , MIC741. RM741.SN72741.etc. e 'TUP' or 'TUN' (Transistor, Universal, PNP or NPN respect- ively) stand for any low fre- quency silicon transistor that meets the following specifi- fT. n - lABCl Some 'TUN's are: BC107. BC108 and BC109 families; 2N3856A, 2N3859, 2N3860, 2N3904, 2N3947. 2N4124. Some 'TUP'S are: BC177 and BC178 families; BC179 family with the possible exeption of BC159 and BC179; 2N241 2. 2N3251 . 2N3906. 2N4126. 2N4291 . e 'DUS' or 'DUG' tOiode Univer- sal, Silicon or Germanium respectively) stands for any diode that meets the following specifications: DUS 25V 100mA IpA 250mW 5pF DUG 20V 35mA 100 pA 250mW IQpF Some 'DUS's are: BA127. BA217, BA218, BA221 . BA222. BA317, BA318. BAX13. BAY61 . 1N914. 1N4148. Some 'DUG's are: OA85. OA91 . OA95, AA116. e 'BC107B', 'BC237B’, BC547B' all refer to the same 'family' of almost identical better-quality silicon transistors. In general, any other member of the same family can be used instead. BC107 (-8. -9) families: BC107 (-8. -9). BC147 (-8. -91. BC207 1-8, -9), BC237 (-8, -9), BC317 (-8. -9), BC347 (-8. -9). BC547 (-8. -9). BC171 (-2.-3), BC182 (-3, -4). BC382 (-3. -4). BC437 (-8. -9), BC414 BC177 (-8, -9) families: BC177 (-8. -9), BC157 (-8. -9). BC204 (-5. -6). BC307 (-8. -9). BC320 (-1, -2), BC350 (-1, -2), BC557 (-8. -9). BC251 (-2. -3). BC212 (-3, -4). BC512 (-3, -4), BC261 (-2. -3). BC416. Resistor and capacitor values When giving component values, decimal points and large numbers of zeros are avoided wherever possible. The decimal point is usually replaced by one of the following abbreviations: p (pico-l * 10'” m Imllli-) - 10” k (kilo-) * 10 ’ M (mega-) = 10‘ G (giga-> = 10* A few examples: Resistance value 2k7: 2700 il. Resistance value 470: 470 n. Capacitance value 4p7: 4.7 pF, or 0.000000000004 7 F . . . Capacitance value lOn: this is the international way of writing 10,000 pF or .01 pF, since 1 n is 1 0' * farads or 1 000 pF . Resistors are Vi Watt 5% carbon types, unless otherwise specified. The DC working voltage of capacitors (other than electro- lytics) is normally assumed to be at least 60 V. As a rule of thumb, a safe value is usually approxi- mately twice the DC supply Test voltages The DC test voltages shown are measured with a 20 kl 7/V instru- ment. unless otherwise specified. U, not V The international letter symbol 'U' for voltage is often used instead of the ambiguous 'V'. 'V'is normally reserved for Volts'. For instance: U b = 10 V, not V b = 10 V. Mains voltages No mains (power line) voltages are listed in Elektor circuits. It is assumed that our readers know what voltage is standard in their part of the world! Readers in countries that use 60 Hz should note that Elektor circuits are designed for 50 Hz operation. This will not normally be a problem; however, in cases where the mains frequency is used for synchronisation some modifi- cation may be required. Technical services to readers • EPS service. Many Elektor articles include a lay-out for a printed circuit board. Some - but not all - of these boards are avail- able ready-etched and predrilled. The ’EPS print service list' in the current issue always gives a com- plete list of available boards. • Technical queries. Members of the technical staff are available to answer technical queries (relating to articles published in Elektor) by telephone on Mondays from 14.00 to 16.30. Letters with technical queries should be addressed to: Dept. TQ. Please enclose a stamped, self addressed envelope; readers outside U.K. please enclose an IRC instead of stamps. • Missing link. Any important modifications to, additions to, improvements on or corrections in Elektor circuits are generally listed under the heeding 'Missing Link' at the earliest opportunity. contents elektor may 1979 - UK 5 Supplement: BASIC (part 3), an introduction to a simple computer language. The desire to have a distinc- tive 'sound' is not restricted to musicians. People are also getting tired of old-fashioned doorbells, and even gongs and chimes are by no means unique. In this issue, a random tune doorbell and a musical doorbell are de- scribed; next month we will extend the range with a fully programmable doorbell. (p.5-17 and p. 5-47) 'Cheep cheeper' was also considered as title for the simple sound effects genera- tor. However, this name doesn't quite do justice to a unit that can produce so many recognisable and unrecognisable noises! (p. 5-32) The BASIC microcomputer card contains three relatively independent sections: a fully buffered and self-contained CPU, a NIBL interpreter in ROM and a standard interface. Adding one 4 K RAM card converts it into a complete microcomputer. (p. 5-34) elektor This month's cover illustrates the possible uses of the pro- grammable timer/controller: control of lighting and (central) heating, domestic appliances such as washing machines and cookers, coffee percolator or early-morning tea, etc. In general: auto- matic switching of equipment at fixed, preset times. contents selektor 5-01 programmable timer/controller 5-08 The circuit described is a versatile timer/controller, capable of switching 4 separate outputs on or off at 4 pre-programmed times every day. The circuit is ideally suited for the control of domestic appliances such as cookers, central heating, intruder alarms (to be switched on at night) etc., or can be used as a straightforward 24 hour 'radio-snooze-alarm' clock. switching mains-powered equipment 5-13 If mains powered equipment is to be switched on and off by electronic circuits like the timer/controller, something more is required: an (electronic) relay. Four examples of this type of reliable and silent electronic relay are described. random tune doorbell ( a. Houghton) 5-17 delay lines (2) 5-18 Having dealt with reverberation and echo in a previous article (see Elektor 46, February 1979) we now take a look at how delay lines can be used to achieve a wide variety of interesting special effects such as double tracking, vibrato, phasing, chorus etc. CAPITALS from the ASCII keyboard 5-24 When programming in BASIC, only capitals are required. This option can be selected by adding one switch on the ASCII keyboard. interface for /iPs 5-25 The specifications for a serial interface between computer and terminal are given by the so-called RS232C and V 24 standards — among others. Only a few components are required for a 'standard' interface. The circuit described in this article can be used in conjunction with both the Elektor SC/MP system and the popular KIM 1. sweep generator (l. Koppen) 5-28 Determining the frequency response of an amplifier normally requires a series of carefully conducted test measurements, a large supply of graph paper, and plenty of patience. How- ever if one possesses an oscilloscope, there is a way of dis- playing frequency response curves upon its screen - provided one also has the instrument described here, namely a sweep generator. simple sound effects 5-32 Using only two CMOS ICs, a wide range of sounds can be produced - varying from an American police siren to the twittering of birds. BASIC-microcomputer ...... 5-34 It seems safe to assume that the 'BASIC microcomputer' is the cheapest home-construction computer ever described that can be programmed using a higher programming language. The BASIC computer consists of not more than two Euro- cardsized printed circuit boards! NIBL-E (D. Hendriksen) 5-43 A BASIC interpreter for the SC/MP has been available for some time. However, this can only be used in systems where page 0 is available for storing the interpreter program. In the Elektor SC/MP system, part of page 0 is used for the monitor program. Even so, an adapted version can be incorporated into the Elektor system — as described in this article. musical doorbell il. witkam) 5-47 market 5-48 advertisers index UK-22 Our remarkable sense of pitch (Dr R. A. Henson*) To hear or sing even the simplest of tunes we need a sense of pitch. Our ability to judge it consistently is re- markable, but investigating how we do it is far from simple. Although we have quite a lot of information about the way the ear responds to sounds at various frequencies, we know very little yet about the subsequent central processing by the nervous system and the brain. Ihc pitch of a sound means its position on a scale of frequencies. Pitch sense is involved in perceiving all complex sounds; for example, human speech has its set of pitches. In this article the way pitch relates to music is considered. In general, the pitch of a tone depends on its fundamental frequency, which determines whether it stands high or low on the musical scale. We tell one tone from another by their different fundamentals. Music is made up of a succession of tones and combinations of tones that are perceived, analysed and coded by the nervous system in ways to be explored, but questions of tuning and scales and how well we can hear them must be dealt with first. Orchestral pitch is agreed nowadays as 440 Hz for A', that is, the note A above middle C. It became necessary to agree this internationally because different pitches were used in different places and because a progressive heightening of pitch in the 1 9th century led to A' as high as 461 IIz in some places. Musical scales are sets of pitches arranged in such a way that they contain a maximum of consonances, where various tones blend pleasingly, and a minimum of dissonances, where they do not. Tuning in 'equal temperament’ has held the field in western music for three centuries because, unlike the earlier ‘perfect temperament’, it makes possible the use of all 24 keys (C major, C minor, C sharp and so on) without retuning. In equal temperament the octave is divided into 1 2 logarithmically equal steps of frequency, each to a frequency 5 .9 per cent greater than the step below. The steps, called semitones, are each divided into 100 further equal steps or cents, and an octave covers 1200 cents. This method of tuning is imperfect and less accurate than the earlier forms. As Balbour, the eminent American composer and organist wrote, ‘all players and singers are playing false most of the time ... these are errors of equal temperament.’ Have we an inbuilt tuning system? Training and early exposure to musical stimuli make this question impossible to answer with assurance. However, we can say that the western musician’s internal pitch scale corresponds to equal temperament but with a slight tendency to sharpen all notes relevant to the tonic or keynote; the target pitch for notation is a shade sharper than equal tempera- Normal Capability How much of the normal range of frequencies is actually heard depends on the age of the hearer and also on what is meant by ‘hearing’ a frequency. Some organ pipes are felt rather than heard. The figures commonly given are 16-20 000 Hz for young people and 20-16 000 Hz for adults. Hearing is most sensitive for frequencies between 1000 and 3000 Hz, being much reduced in the extreme lower and higher ranges. People’s ability to discriminate in pitch ranges from those who are tune- or tone-deaf to those with absolute pitch sense. Though it is highly developed in some, there is no experimental evidence that they can do better than discrimi- nate between quarter tone intervals consistently. The ability to detect small changes of frequency diminishes sharply above 4000 Hz. Some writers speak of tone ‘height’ and tone ‘chroma’. Tone height means pitch, whereas tone chroma indicates the col- our or the way in which a tone affects a listener. It has been suggested that tone chroma plays a part in pitch identifica- tion, but Roederer** believed that there was no psycho-acoustic foundation for the notion, because all intervals are equal in the tempered scale; only the pitch is different. Maybe this is a meta- physical question, but there must be few musicians who would agree that C major sounds the same as E flat major. A sense of relative pitch is necessary for hearing or singing a simple tune. Most of us perceive and remember music in terms of changing sequences of pitch rather than in orchestral or other pitch values. Absolute or perfect pitch is the ability to name a sounded note or iden- tify its frequency, or to do both this and to sing a given note accurately straight off. Possessors of absolute pitch appear to have an inbuilt pitch grid against which to measure incoming sounds, though there may be consider- able lability or flexibility in the pitch reference points from day to day, for example, at the menstrual periods. There has been a prolonged debate about whether absolute pitch is innate or acquired, but the present majority view is that both heredity and environ- ment play their parts. Early training is needed for the development of absolute pitch, and important requirements prob- ably include lengthy exposure to sounds of constant frequency and single, criti- cal pitch experiences. Absolute pitch may be the normal manner in which we deal with frequency, but this is trained out of us by our musical environment, which depends on relative pitch. Cer- tainly, absolute pitch can be learned in early childhood, but while pitch percep- tion can be improved in adults by train- ing, no one has been able to train ado- lescents and older people who had little original ability in pitch-naming. It is likely that highly developed pitch- naming almost always derives from rein- forcement of a child’s behaviour by an adult. Perfect pitch is an advantage in some aspects of practical musicianship, but it also carries handicaps. For example, a singer has to transpose consciously when a key is changed. Interestingly, all * Neurological Department, the London Hospital. ** J. G. Roederer, Professor of Physics at the University of Denver, Colorado, USA. normal people can retain information on absolute pitch for periods ranging from ten seconds to a few minutes, but the information is then discarded. Pitch Perception Musical notes must be sounded for at least two or three cycles before their frequencies can be precisely determined. The ear and the brain are more suscepti- ble to the pitch changes of a melody than to blurred acoustic patterns, such as a glissando by a pianist. Problems of tuning and intonation must also be taken into account. Electronic analysis has shown that professional violinists and woodwind players deviate slightly from equal temperament in tuning or playing their instruments, and these deviations differ from one player to the next. In other words, they do not all play the same frequency for given notes. Fortunately, the auditory processing mechanism of the ear ignores minor fluctuations in pitch so that we place tones clearly in their right category. When fluctuations are larger the tone may seem out of tune, with the appear- ance of beats of one frequency against another, or be perceived as the next semitone or tone above or below the desired pitch. Considerations of this sort brought the suggestion that pitch may be defined operationally as the subjec- tive correlate of each one of the audi- tory events contained in a musical per- formance. The Peripheral Analyser The capacity of the human ear to ana- lyse sound waves is truly remarkable. Perception of musical sound depends on several factors, including identifica- tion of the pitch, duration, intensity and rhythm of a series of tones, and this requires an efficient peripheral analyser of the sound waves produced. Here we are concerned solely with the problem of pitch perception. Many theories of pitch discrimination have been advanced over the past hun- dred years, but even now a unified solu- tion escapes us. Current knowledge and views appear to add up to what follows. Sound waves are transmitted from out- side via the ear-drum and the ossicles of the middle ear to the round window membrane, which sets up pressure changes in the cochlear fluids of the inner ear. The sound receptors of the cochlea are the inner hair cells, disposed along the basilar membrane. These cells are activated by a travelling wave which always passes throughout the membrane from the base to the apex of the coch- lea. The travelling wave has its greatest amplitude at a point determined by the frequency of the sound stimulus. High frequencies cause vibrations in a small part of the base of the cochlear parti- tion; low frequencies set the whole membrane into vibration. The place where the inner hair cells are activated may well account for the perception of high frequencies, and this idea is sup- ported by the fact that people with disease at the base of the cochlea are deaf to high tones. But this theory does not explain how we perceive low tones, and it has been suggested that low fre- quencies are represented by the rate of nerve impulses engendered by the stimu- lus. The cochlear nerve fibres, which join the ear to the brainstem, cannot carry more than 500 to 600 impulses per second, and this led to a ‘volley’ theory. This was that groups of fibres could carry frequency information, so that the stimulus frequency is repre- sented in the combined pattern of nerve impulses produced. This idea is accept- able in a general sense, but there are objections to it on physiological grounds, especially where frequencies over 3000 Hz are concerned. Perhaps place and frequency and patterns in time all play their parts in pitch percep- tion. Harmonics may help in identifying the fundamental of lower tones, for if a set of overtones is sounded, without the fundamental, the listener’s ear supplies it and he hears it just the same. Second Mechanism This first stage of analysis by the basilar membrane is not enough to account for the fine degree of pitch discrimination achieved by the human ear. Studies on the mechanical tuning of the basilar membrane have shown that it acts as a heavily damped, broadly tuned struc- ture; on the other hand, recent record- ings of the activity of a single auditory nerve fibre have shown that the tuning here is sufficiently fine to meet psy- chophysical requirements. There must be a second mechanism inside the coch- lea to account for the difference in tuning between the two structures, and it has been suggested that the olivo- cochlear bundle, which runs from the brainstem to the inner ear, is involved in it. With higher intensities - for exam- ple, the orchestral fortissimo — the neural tuning of the cochlea is broad, and it seems that there must be a fur- ther tuning mechanism within the ner- vous system to deal with loud sounds. Single auditory neurons have their own best frequencies, but they can also respond to neighbouring frequencies; that is to say, the frequencies that neurons respond to overlap. Looking at how the system works, an arrangement of this type would be essential to ensure the transition from one sound to another that listening to music demands; it would also contribute towards the appreciation of loudness. Psychophysical studies suggest that fre- quency selectivity is achieved in man by the equivalent of a bank of overlapping filters, a system that would separate the individual components of a complex signal for analysis. Psychophysical mea- surements, known as critical bands, have been used to find the effective band- widths of the human auditory system. It appears that these critical bands range from 200 Hz wide at 1 kHz to 2 kHz wide at 10 kHz. Such a mechanism could explain why we hear the normal differences in tuning or sounding of instruments or voices as the same note or tone. Tonal material that is not rele- vant to the task on hand is inhibited, a process called tuning or sharpening. The exquisite sensitivity of the human ear is shown by the way in which we can sepa- rate simultaneously-heard tones with shared harmonics. So far we have been unable to sort out the mechanisms that produce these psychophysical effects. A central pitch processor should trans- form incoming nervous impulses bearing information on pitch into patterns, so that all stimuli of the same periodicity are represented in the same way. This would produce individual sensations for different pitches. We have already seen the need for an auditory system capable of categorical assessment and of dealing with tones of neighbouring frequency or shared harmonics. The nervous system meets this need in ways we do not understand. The auditory system must integrate stimuli presented to both ears, and its ability to do this is shown by the way harmonic components of a tone fed simultaneously into both ears combine so that the subject hears the fundamen- tal. Conventional neuroanatomical and neurophysiological studies have given little information about central pitch processing, although the complex path- ways of hearing in the brainstem have been thoroughly described. Auditory nerve fibres from both inner ears stream up the brainstem on both sides after their first relay point in the cochlear nuclei. It appears that these fibres relay at four or more points in the brainstem nuclei before they reach the auditory cortex of the brain. The final relay is in the thalamus, and from it auditory radiation flows to the auditory cortex. Apart from the com- plexity of the nuclei and linking tracts, investigations are made difficult because if anaesthetics are used; then evoked auditory responses in man and experi- mental animals are not normal, but, of course, more of these abnormal responses are obtained under anaes- thesia than otherwise. In general, how- ever, we can say that the organization that the cochlea imposes on frequency is maintained through the nuclei of the brainstem to the thalamus and auditory radiation. Experimental work on the cat has shown that there is systematic cochlear representation in the primary auditory cortex, but opinions differ on whether the techniques used show the true state of affairs at this level. The Auditory Cortex The primary auditory cortex, that is the part of the brain solely concerned with input from the cochlear system, lies on an area surrounded by secondary cor- tex. In animals, this secondary cortex also appears to generate some syste- matic representation of pitch frequen- cies. The auditory cortex differs in some respects from other parts of the cortex, but the nerve cells are disposed in the usual columnar arrangement. Many of these cells are finely tuned and the num- ber activated increases with sound inten- sity. The nerve cell population is not uniform, nor would we expect it to be because of the complicated input, carry- ing various information about sounds heard. Descending pathways from the cortex pass to those nuclei in the brain- stem concerned with hearing. These pathways can be expected to shape and control pitch input by inhibiting and amplifying signals to ensure, among other things, that dominant frequencies prevail. There is evidence from observa- tions on people with brain damage from strokes that humans can distinguish pure tones of different frequency with- out the intervention of the auditory cortex. But such patients cannot recog- nize complex sounds. We do not know how the brain deals with auditory input. On general princi- ples we may presume that incoming nervous impulses are analysed for such variables as pitch, duration, rhythm, intensity, sequence and location. This analysis is not confined to the cells in the immediate area of projection; neigh- bouring groups and columns of cells arc also involved. After analysis comes syn- thesis. Within the cortex new pitch experiences, arriving as coded patterns of nerve impulses, are matched against the old, and the incoming stimuli are compared and contrasted with each other. Further consideration of central pitch processing would involve discussion of psychological and psychophysical ideas which are beyond the scope of this arti- cle. However, we may conclude with the thought that many factors are involved in pitch discrimination, including semantic memory, musical memory, prediction and set and bias. Progress in our knowledge of the ways in which peripheral analysis of pitch takes place can be expected in the next few years. Solution of the problems of central pitch processing is likely to take much longer. Cassette Recorder with a brain Cassette decks used to be low-fi, easy- to-operate machines. You just popped in a cassette, hit the Record button and set the level. Over the years, however, they’ve been progressively upgraded; new types of tape have been introduced; noise reduction systems have been added. The result: cassette decks are now hi-fi - but they are anything but easy to operate One of the main problems is the vast difference from tape to tape. Modern decks have an array of buttons that select the (hopefully) optimum bias setting and equalisation characteristics for various types of tape (Fe, Cr0 2 , FeCr, etc.). In practice, even this isn’t enough to get the best out of the system, owing to the differences between even nominally identical tapes. A difference in sensitivity of one or two dB between, say, two Cr0 2 tapes may not seem much - but if some kind of noise reduction system is used, any errors of this type will be aggravated. So what do you do? Add more buttons? Or, worse still, add continuous controls? For most users, this would make matters worse instead of better — the chance of finding the ‘correct’ setting will decrease in proportion to the number of controls. JVC have come up with a better solution: enlist the aid of our new- found friend, the microprocessor! In their new top-of-the-line cassette deck, the KD-A8E, top quality recordings can be made after an initial twenty-second alignment procedure that is carried out by the machine itself, fully automati- cally. After a cassette has been inserted. the so-called BEST system (for ‘Bias, Equalisation, Sensitivity and Total’) first selects the optimum bias setting for that particular tape. It then pro- ceeds to select the correct equalisation and sensitivity settings for a flat 0 dB frequency response out to 1 0 kHz - worst case, that is, using standard tape! What it does Having loaded a cassette and operated the ‘computer start’ button, the sequence of (automatic) operations are as shown in figure 1 . The first thing is to get past the tape leader and into the tape proper, so: ‘Fast Forward Wind’ for 1.5 seconds. The machine now switches to Record. After erasing 2.5 seconds worth of tape to leave a gap, two ‘index markers’ are recorded: 60 ms pulses at -5 dB. A 1 kHz reference signal is then recorded at - 1 5 dB, followed by a 6.3 kHz signal at the same level. During recording of this 6.3 kHz signal, the bias level is reduced in 32 steps - each step lasting 60 ms — from 30% above the ‘average’ bias level to 30% below. Now, the tape is rewound to the blank section and the test sequence is played back; the ‘optimum’ bias setting is the one that is found to give identical levels for the 1 kHz reference and the 6.3 kHz test signals. During this bias setting procedure, the noise reduction circuits are by-passed and the frequency equalisation is set at an average level for that particular kind of tape. It is now time to ‘fine-tune’ this equalisation. A further test section is recorded, consisting of two index markers, the 1 kHz reference signal and 1 (Spectrum 156) 5-04 - elektor may 1979 selektnt __asaaani a set of 10 kHz test signals. As these 1 0 kHz sinewaves are recorded, first right channel only and then left channel only, the equalisation for the correspon- ding channel is increased in eight steps. Finally, it is useful to set the recording sensitivity at the 'standard 0 dB’ level — if only to make sure that noise reduction systems work properly! - and so the 1 kHz signal is recorded in sixteen level steps. The tape is now rewound and played back. The equalisation settings for both channels that give equal levels for the 1 kHz reference and 10 kHz test signals are selected; the 1 kHz test signals are compared with the original signal level to select the sensitivity setting that gives 0 dB overall gain. Finally, the machine winds the tape back and signals that it’s ‘ready to go’. How it does it As stated earlier, the whole system works under microprocessor control. The ‘program’ is illustrated in the flow chart (figure 2); most of it should be clear from the description given above. Starting at the top, the computer first wants to know whether or not its assistance is required. If the ‘automatic flag’ is not set, the bias, equalisation and sensitivity are simply set at ‘nominal’ levels, as in any normal cassette recorder. Assuming, however, that the flag is ‘on’ and the ‘computer start’ button is operated, the sequence of events described earlier is initiated: Fast Forward wind; RECord gap, markers, 1 kHz reference and 6.3 kHz test with varying bias; REWind and Play, Bias Select. At this point, a step is introduced that has not yet been mentioned: Error detection. In the description given so far, we have blithly assumed that an ‘optimum setting’ for the various parameters will always be found. In practice, of course, this need not always be the case: the first section of tape may be damaged (causing severe drop-outs) or the tape characteristics may be outside the range of automatic adjustment. If this happens, the machine first checks whether this is its first try; if so, it repeats the whole procedure without first rewinding - so that the test signals are recorded on a new section of tape. If an error again occurs, it gives up and lights a flashing ‘error indicator’. Assuming that no error has occured the bias is then correctly set - the next step is to record the equalisation and sensitivity test signals. The optimum settings are then selected; once again, if an error is detected the machine will have one further try. If the setting-up procedure has been completed without problems, the machine will rewind the tape and indi- cate that calibration is complete. 1 HEW a PloTl Table 1 SPECIFICATIONS * Frequency Response (Recording/Playback at —20 VU) (Normal tape) 15 Hz - 17,000 Hz (SA/Cr0 2 tape) (30 - 12,500 Hz ± 1 dB) 15 Hz - 18,000 Hz (Metal tape) (30 - 12,500 Hz i 1 dB) (at OVU: 25 8.000 Hz ±3dB> 15 Hz - 18,000 Hz • Signal to Noise Ratio (30 12,500 Hz l 1 dB) (atOVU:25-12, 500Hz ±3dB) 58 dB (ANRS-off) • Wow & Flutter 0.035% (WRMS) * Channel Separation (DIN 45 500 : 0.14%) 35 dB • Crosstalk 65 dB * FF/Rewind Time 80 sec. • Total Harmonic Distortion : 1.2% • Third harmonic Distortion 0,5% (0 VU, 1 kHz, UD Tape) * Dimensions (W x H x D) 450 x 1 20 x 395 mm * Weight : 11 kg fsn £ ' m ^ I 5-06 - elektor ma y 1979 .rii lJiL L t itili Block diagram In the same way that the flow chart gives a brief outline of the program, a block diagram will give some idea of the hardware involved (see figure 3). The switches and trimming potentio- meters normally used are replaced by or supplemented with electronic circuits that are controlled by the microcom- puter. Of the sections shown in the simplified block diagram, only a few require further explanation. • ANRS or Dolby. This refers to the noise reduction circuit: ANRS is JVC’s own version; Dolby is Dolby. . . • Recording equalisation select and Bias select. These sections are controlled by a three-way switch on the front panel. The first position is correct for both normal and most high-performance tapes (Cr0 2 , SA, XL-II, etc.); the second and third positions are for FeCr and metal tape, respectively. The correspon- ding equalisation characteristics are reasonably accurate for the various types of tape. • Tape counter. Rapid and relatively precise ‘tape position’ information is obtained from a Hall device mounted on the mechanical tape counter: its output is fed to a counter in the microcom- puter. Results The main specifications are given in table 1 . It must be realised that these are ‘guaranteed worst-case specs’ - not just ‘what you may achieve if you’re lucky enough to use an ideally suited tape’ .... A single test may serve to illustrate this. In figure 4a, the frequency response of a standard tape is shown - as obtained with the preset equalisations and sensitivity adjustments. As can be seen, the response in this case is 2 dB down at 3 kHz and 4 dB down at 15 kHz. Not bad? Figure 4b shows the response that can be obtained with the same tape - after the computer has done its job! It might be argued that the same result could be obtained with more accurate preset adjustment. Not so. As shown in table 2, the recording sensitivity at 1 kHz can vary by as much as 2.6 dB for ‘high quality’ tapes, and this can have a distinctly noticeable effect on the fre- quency response if a noise reduction system such as Dolby or ANRS is used. Furthermore, the variation in frequency response for 12.5 kHz signals with respect to the 1 kHz level may vary by as much as 4.7 dB for nominally ‘iden- tical’ tapes. Even if the effect of a noise Table 2 Sensitivity and frequency characterictics of tapes Tape No. Sensitivity Freq. Response Normal 1 -0.4 0 2 -0,7 -0,2 3 -0,1 + 0.1 4 -0,8 -0,7 5 0 -1,6 6 -0,7 + 1,7 7 -0.7 + 0,1 8 + 0.6 + 3,1 9 0 + 2,8 Deviation 1,4 4,7 Cr0 2 10 + 0,9 -1.5 -1.2 + 0.2 12 + 0,9 -1,6 13 + 1,4 + 1,1 Deviation 2,6 2,5 reduction system is disregarded, it is impossible to guarantee a response within ± I dB if only preset adjustment is used! One final point. The full and honest specifications, as presented by JVC, may appear less than sensational in some aspects. The frequency response at 0 VU, for instance, seems rather poor; however, when recording ‘normal music’ this is irrelevant — the -20 VU response is more important for high fre- quencies. Similarly, distortion and signal-to-noise ratio (without ANRS!) may seem marginal, but they are in fact quite good for a compact cassette system. As J. Moorer put it at the recent AES convention in Brussels, when addressing representatives of the recording industry (amongst others): ”If we could get more on the tape, you would reduce the track width or the tape speed, wouldn’t you? You’ve been doing it for years!” True enough — witness the compact cassette. Victor Company of Japan (JVC) Limited, European liaison office Kiesstrasse 20 6 Frank furt/M. 90 West Germany. 1466 S) The shape of things to come? A fully decoded 256 x 4 bit non-volatile (! ) random access memory has been announced by General Instrument Microelectronics Ltd. This RAM/ F.AROM, designated the ER171 1, is intended for applications where data is constantly changing and must be pro- tected in case of a power failure. The device operates normally as a RAM with a 1.5 micro-second cycle time. When powering down, a si ngle ne gative pulse applied to the Erase/Write control line elektc 1979 -5-07 .ESSiUJUIli enters the entire contents of the 1024 bit memory into associated on-chip EAROM cells. All stored data is retained for 72 hours minimum after a 1 milli- second write pulse, or 30 days minimum after a 10 millisecond write pulse. Data can be recalled (restored into the RAM cells) by means of a power-up sequence followed by a bulk erase of the EA ROM cells (a positive pulse on the Erase/Write control iine). The HR 1 7 1 1 is directly compatible with 4-bit microprocessors and typical appli- cations include protection of process control state variables during power interruptions, machine and motor con- trol to hold set points and feedback data, navigation equipment to hold constantly varying time and position data and cash registers for holding con- stantly changing cash totals. The ER171 1 is available in both ceramic or plastic 22 pin dual-in-line packages. General Instrument Microelectronics Ltd, Regency House, 1-4 Warwick Street, London W1R 5WB. U.K. (465 S) broadcast system which allows a com- puter to put together human speech. The system has been adopted by the UK Civil Aviation Authority and will be used to transmit in-flight weather reports from the summer of next year. Marconi says it has recorded the voice of one of its executives, Colonel John West, reading a range of standard weather report phrases, words and figures. These are converted into digital form and stored in a computer bank. When the computer is fed the latest telex report it automatically produces and arranges the sequence of words, phrases and figures needed to create a human voice report. Marconi, which has more than 20 years' experience in voice digitization for military use, believes this technique will be adopted for much wider use. For example, practically all broadcast announcements at airports and main- line railway stations could be constantly updated and issued by automation. (470S) This is your computer speaking Pilots flying in and out of Britain’s main airports next year will be helped by a computer with a human voice. The latest weather information about conditions at airports in Britain and continental Europe is vital to airline operations. Weather reports arc trans- mitted continuously from the UK Civil Aviation Communications Centre at London's Heathrow Airport. These reports are based on information which is being continually updated and received every half-our from all over Europe by telex at the Heathrow centre. At present each report has to be read by a member of the centre staff and re- corded before being transmitted by radio to the hundreds of pilots who daily use UK airspace. Modem technology now makes it possible for a mechanical voice to be created by a computer but this produces a science-fiction-like voice with a mono- tonous tone. UK system will operate in 1980 Britain’s Marconi space and defence systems company believes it has found the answer with a new automatic 15 kHz is enough for Golden Ears! Everyone ‘knows’ that 20 kHz bandwidth is necessary for top-quality audio reproduction. Is it, though? For some time now, ‘necessary bandwidth’ has been the subject of heated discussions in the professional audio world. The main reason for the sudden interest is the advent of digital audio. In digital systems, the audio signal must be ‘sampled’, and the sampling frequency determines the bandwidth. The sampling frequencies proposed vary between 32 kHz and 54 kHz - corresponding to theoretical audio bandwidths between 1 6 kHz and 27 kHz. At this point, the battle is joined . . . Proponents of 32 kHz (broadcasting authorities, in particular) maintain that ‘nobody heard the difference when we experimented with digital audio at a 32 kHz sampling rate’. ‘No great trick’, say the opponents, ‘you’ve been using sharp 15 kHz low-pass filters for years’. Manufacturers of digital audio recorders introduce a new consideration: ‘We can’t sell digital recorders unless they at least equal the specs of conventional analog equipment. A bandwidth of well over 20 kHz is therefore essential’. At last year’s AES convention in Hamburg, several groups announced that they were going to run tests to find the true bandwidth requirement for top-quality audio. This year, in Brussels, the results of some of these experiments were reported. One typical test series can be briefly described as follows. A special test signal, containing harmonics at almost full level to well over 25 kHz, was reproduced via suitable loudspeakers (ionophones). A group of critical listeners (recording engineers and other ‘Golden Ears’) were used as Guinea pigs. Several low-pass filters were evaluated, with cut-off frequencies of 1 5 kHz, 1 8 kHz and 20 kHz, with filter orders varying from 7th to 1 3 1 * 1 order and with and without group delay correction. Two loudspeakers were used; the signals could be the same (both filtered or both unfiltered) or one signal could be the original and the other after filtering. The test subjects were asked to determine, by A-B comparison, whether or not there was any difference in the two signals. Note that no attempt was made at quality evaluation; the only question was: ‘Can you hear any difference between the two signals?’. Since the only possible answers are Yes’ and ‘no’, random guesses would produce 50% accuracy. A ‘significant’ difference in this type of test is generally taken as more than 75%. The results were perhaps somewhat surprising . . . Even with the ‘worst possible’ filter combination (15 kHz cut-off, 13 th order, no group delay correction and two of these filters used in cascade), the percentage of ‘correct’ answers was only 62% for the most critical section of the test group. The percentage for the whole group was only 57%! The conclusion drawn is that, even with a 1 5 kHz filter, differences will only be heard in extreme cases : signals with an extremely strong high-frequency content ; a sufficiently broadband loudspeaker; listeners with exceptionally good hearing; and, finally, the possibility of direct signal comparison. An unlikely combination . . . It will be interesting to see the reaction in professional audio circles to these claims. Will it be ready acceptance (‘OK, that’s settled’), dogmatic refutation (‘I don’t believe it’) or a call for further tests? It is interesting to note that at least three groups have already reached very similar conclusions: a representative of the broadcasting authorities, a record manufacturer and a manufacturer of digital audio tape recorders who has also introduced a digital audio disc system . . . Based in part on AES preprint 1449, presented at the 62 n d AES convention: ‘What bandwidth is necessary for optimal sound transmission?’. G.H. Plenge, H. Jakubowski and P. Schone. 5-08 - elektor may 1979 programmable timer/controller programmable timer/controller The circuit described here is a versatile timer/controller, capable of switching 4 separate outputs on or off at 4 pre-programmed times every day. The circuit is ideally suited for the control of domestic appliances such as cookers, central heating, intruder alarms (to be switched on at night) etc., or can be used as a straightforward 24 hour 'radio-snooze-alarm' clock. Almost all the work is performed by a single 1C, so that the circuit is both compact and relatively inexpensive. Table 1. * 24 hour real-time clock with 4-digit display * 4 control outputs * 4 programmable set point times with repeat every 24 hours * valid day programming to skip certain days if desired * manual mode to verify programming * each output can switch up to 400 mA The heart of the circuit is formed by the MM57160 standard timer and controller (STAC) chip from National Semi- conductor. This IC is designed for use in timing applications where up to 4 separate outputs are required to operate at up to 4 user-programmed times. Thanks to direct display drive capability and on-chip keyboard scan facility, very little in the way of external hardware is required to provide a complete timer/ controller system. The main features of the IC are summarised in table 1 . An interesting facility is the provision of valid day programming, which allows control outputs to be inhibited on certain days (weekends, for instance). Circuit design The circuit diagram of the timer/ controller is shown in figure 1 . Timing is derived from the 50 Hz mains fre- quency at the secondary of the trans- former and shaped by Nl, N2 and N3. Mains transients are suppressed by the interference filter Rl/Cl. During the positive half cycle of the 50 Hz input signal C2 is rapidly discharged by Nl. The capacitor takes much longer to charge up again, however, since this can only occur via R3, which is roughly 1000 times greater than R2. The condition of each of the four outputs of the timer/controller chip (IC 1 ) is indicated by a LED. Each output has a current capability of 20 mA but buffers are included to in- crease the maximum load current to 400 mA. It must be remembered that the use of the buffers inverts the output levels i.e. if the control output is low (0V) then the buffer output will be high (equal to + supply). This should be borne in mind when programming the system. A stabilised power supply is provided, using a 78L08 regulator IC. Com- ponents R7 and C3 are included to ensure that the timer is reset upon switch-on. Initial conditions are: (real time) clock to 00 : 00; all set point times to 00 : 00 and all outputs off; all days valid; and the IC in the real time clock mode. Programming Programming is carried out using push button switches having up to three different functions and these are summarised in table 2. Set point times (switching times) are loaded as follows: • The DATA ENTRY switch is momen- tarily depressed to take the system from the real time clock mode to the data entry mode, whereupon one of the set point times is displayed and its outputs status indicated on the decimal points of the display. If the data entry mode is selected immediately after power-up, the display will show 00 : 00, with the decimal points off. • To examine the next set point, the ADVANCE SET POINT switch is depressed. The four set point values are stored in a revolving stack, so that four advances will cause the stack to roll round to the original value. • Set point times are loaded or altered using the SET HOURS and SET MINUTES switches. When depressed, these switches increment the hours displays from 0-23 and the minutes displays from 0-59 at a rate of one per second. • Next, the SET STATUS switch is used to program the output(s) to be activated at the set point times. When the SET STATUS switch is initially depressed the first decimal point is turned on, signifying that output 1 will be activated at this time. • If this is the only output to be activa- ted, the ADVANCE SET POINT switch can be depressed to go on to the next set point. • If, however, output 2, 3 or 4 is to be activated, the SET STATUS switch should be pressed again to advance to the subsequent outputs. Each advance turns off the previous decimal point (and output). • If more than one output is to be ac- tivated, e.g. 2 and 4, the HOLD STATUS switch is used to hold num- ber 2 decimal point on before the SET STATUS switch advances through 3 to number 4. Thus using the SET STATUS and HOLD STATUS switches it is possible to program any combina- timer /controller elektor may 1979 — 5-09 Figure 1. Complete circuit diagram of the tion of outputs to be activated at each is displayed in the left-most display timer/controller, if desired, the output set point. digit and the validity of the day in the buffers N4 . . . N7 may be omitted. • [f an error is made during program- right-most digit. A valid day is signified ming, operating the SET STATUS by ‘1’, an invalid day by ‘O’. When switch from position 4 will clear all depressed in the day mode, the SET data (including that set by HOLD DAY switch advances to the next day. STATUS), whereupon the correct in- The validity information can be altered formation can be re-entered. by the SET STATUS switch. To return • The programmed information can be to the real-time clock mode the DAY verified by using the MANUAL switch, MODE switch is pressed a second time, which, when depressed in the data • With the aid of the HOLD STATUS/ entry mode, transfers the decimal point DEMO switch it is possible to rapidly status to the outputs, activating the cycle through the entire programmed appropriate relay, solenoid, etc. The sequence. When this switch is pressed system is returned to the real-time i n the real-time clock mode, the clock clock mode by depressing the DATA advances at a rate of one hour per ENTRY switch a second time. second, i.e. a 24 hour day can be verified • To examine and alter the valid day in 24 seconds, whilst a 7-day week information, the DAY MODE key is requires less than 3 minutes to check, depressed, whereupon the current day • To set the real-time clock to the cor- elektor may 1979 Remote transducer input; forces output 1 ON, out- puts 2-4 OFF until next valid set point after switch Manual verification mode; allows data to be trans- ferred to outputs 1 —4 Allows rapid demonstra- tion of sequence by ad- vancing clock at rate of 1 hr/sec ADVANCE SETPOINT/ RESET TIME 00.00 without changing set points but resets all days to val id Holds output N ON while programming advances to output N + 1, N - 1-4 RETURNS UNIT TO THE REAL-TIME CLOCK MODE Advances display to the next set point so that it may be verified or Controls programming of outputs; resets output N to " 0 " (unless preceded by HOLD key) and ad vances to output N + 1 RETURNS UNIT TO THE REAL-TIME CLOCK Alternate action key; changes day from valid ("1") to invalid ("0") SET HOURS/ Advances hours display elektor may 1979 — 5-1 1 4 HP 5082-7414 1 A A A A A P- 2S£C l rj' V V ‘n’ W *n C, e c C 3 dp C 4 wm a rect time the SET HOURS and SET MINUTES switches are used. The clock time can be reset to zero by pressing the ADVANCE SET POINT switch in the real-time clock mode. The set point times remain unaffected by this opera- tion, however it should be noted that it also resets the valid day information (i.e. all days are valid). • Finally, the MANUAL/REMOTE TRANSDUCER switch provides a facil- ity for external inputs. When pressed in the real-time clock mode, the program- med data is ignored, and output 1 is switched on whilst outputs 2 ... 4 are turned off. On valid days this condition is maintained until the next set point time. On non-valid days all outputs are turned off as soon as the switch is opened. Construction For ease of construction a printed circuit board (figures 2 and 3) is avail- able from the Elektor print service. Since the display is made entirely of plastic it may be unwise to solder it directly to the board but it can be mounted in an IC socket. The pin-out details for the display are given in figure 4 for those readers who may already possess a suitable type. It is often possible to pick up second- hand calculators and to extract the displays from them, thereby saving money. The only condition is that the display must be common cathode. If the pin-out of the display is not known, it is possible to determine it by using a multimeter switched to a resistance range and checking each of the pins in turn to see which segment they light up. Use a discrete LED first to check that the meter is set to the right range. Like the Beatles, some readers may have an application for an 8-day week cycle. This facility can be selected by wiring a switch in series with diode D 1 , or D 1 can be mounted directly on the printed circuit board. Similarly diode D2, if removed from the board will enable the timer to be used with a 60 Hz mains frequency supply. The choice of transformer, bridge rectifier and smoothing capacitor is determined by the maximum current consumption of the circuit, which in this case is 4 x 400 mA = 1.6 A. However, if the load current of each output is known t~ be less than the maximum, it is a simple matter to calculate the desired transformer current rating. As a rule of thumb the value of the electrolytic can be calculated on the basis of 2000 /iF per amp. The values shown in the circuit diagram for the Figure 2. Track pattern of the printed circuit board for the timer/controller (EPS 79093). As can be seen there are a considerable number of connections to the displays and to the keyboard. The use of a printed circuit board reduces the amount of work and in- creases the reliability of the circuit. Figure 3. Component overlay of the printed circuit board. Diode D1, (see text) is shown in dotted lines. If a different type of display is used, then it may not fit on the board, in which case separate connections will be necessary. Figure 4. Pin-out of the HP 5082-7414. The segments are indicated by the small letters, whilst Cl, C2 etc. stand for the cathode of the first display, second display, and so on. Figure 5. Layout of the keyboard. power supply components are sufficient to drive several relays (12 V/20 to 50 mA). The relays, like the LEDs and their resistors, can be connected to the unstabilised supply (positive end of C4). One should check to ensure that the stabilised supply is satisfactory. With a voltage between 8 and 9.5 V trouble- free operation should be guaranteed. There is in fact no need for the supply voltage to exceed 8 V, and if one measures a voltage of more than 8.6 V, diode D3 can safely be omitted. How- ever if for some reason the voltage regulator provides less than 8 V, the diode must be included. Upon switch-on the displays should show ‘0000’. If this is not the case then pin 11 of IC1 should be grounded providing an additional reset pulse. If the display still refuses to reset then there is a fault in the circuit (defective IC, bad solder joint, etc.). It may at first sight appear that pro- gramming the timer is rather a compli- cated process. However with a little practice it is possible to enter and check (using the DEMO and MANUAL switches) a program extremely quickly. The following sample program should help to familiarise prospective users with program entry and operation. 5-12 — elektor 1979 programmable timer /controller i i n „ _ J a > n i *.« J SET STATUS HOLD STATUS SET STATUS HOLD STATUS SET STATUS HOLD STATUS SET STATUS ADVANCE SET 0000 POINT 1400 1405 SET HOURS SET MINUTES SET STATUS TfOLDSTATUS HOLD STATUS SET ST At US SET STATUS 1.405. ADVANCE SET 0000 POINT SET HOURS 1500 SET MINUTES 1501 is displayed. Set point 1 at 14.00 12 p.m.I.outp Hold output 1 ON Output 2 ON Hold output 2 ON Output 3 ON Hold output 3 ON Output 4 ON memory, and at 14.00 hours all foi outputs will be turned on. Switch is depressed until second sei (hours) is displayed. Switch is depressed until correct se (minutes) is displayed. Set point 2 at 14.05 hours (2.05 p. Hold output 1 ON Output 2 ON Output 2 OFF. output 3 ON (second decim point is extinguished, third decimal point ti Switch is depressed until third set point time (hours) is displayed. Third set point time (minutes) is displayed ADVANCE SET 0000 POINT SET HOURS 1600 SET STATUS 16.00 HOLD STATUS 16.00 SET STATUS 16.0.0 SET STATUS 16.00. ), output DAY MODE SET DAY SET DAY SET DAY SET DAY SET DAY SET STATUS SET DAY SET STATUS Output 1 OFF, output 2 ON Hold output 2 ON Output 3 ON Output 3 OFF, output 4 ON. Outpi fourtl DATA ENTRY 0000 Current information to memory. ory, return to real-time clock mode. It would also have been possible to press the ADVANCE SET POINT switch, in which have appeared (i.e” 1 .4.0.0.) The timer is now programmed with valid day information. The first digit indicates the dey, the second digit represents status informatior A non-valid day, therefore . . Return to current day To illustrate how the timer/controller can be programmed, assume that it is required to perform the following operations: 1. Output 1 should turn on at 14.00 and turn off at 16.00 each valid day. 2. Output 2 should turn off at 14.05 and turn back on at 16.00 each valid day. 3. Output 3 should turn on at 14.00 and turnoff at 14.05. 4. Output 4 should turn off at 15.01 and turn on again at 16.00. 5. Valid days are Monday to Friday inclusive. Saturday and Sunday are invalid days. 6. The current day is Monday, the time is 13.00. From the above information we can con- struct the following 'truth table’. time 01 02 03 04 14.00 1111 14.05 1 0 0 1 15.01 10 0 0 16.00 0 1 0 1 The states of each output are illustrated in the timing diagram. To load the above program into the chip memory the following sequence of key SWITCH DEPRESSED DISPLAY REMARKS The program can be checked by pressing the DEMO switch. As soon as this switch is depressed the clock will advance at a rate of 1 hour per second, lighting up the output LEDs in accordance with the program. Remember, however that because of the buffers the LEDs will indicate the inverse of the chip output states. Finally, the clock can be set to the correct current time using the SET HOURS switch. (itching mains-powered equipment 1979 - 5-13 switching mains-powered equipment Electronic relays The programmable timer/con- troller, described elsewhere in this issue, is not really complete. It cannot be used to switch aquarium lighting and heating, for instance — not directly, that is. If mains-powered equipment is to be switched on and off by electronic circuits like the timer/controller, something more is required: an (electronic) relay. The programmable timer/controller will often be required to switch mains- powered equipment. One possibility would be to use the old and trusty mechanical relay, but this does have certain disadvantages. Being mechani- cal, the relay is relatively slow and prone to wear. Furthermore, it is rather bulky. For these reasons, it makes sense to use an up-to-date electronic replace- ment: the triac. In industrial applications, the tendency is to use what is known as a ‘solid state relay’: a triac with associated electronics. Four examples of this type of reliable and silent electronic relay are described here. The circuits are described in order of sophistication; each one can be used to replace mechanical relays, and even the simplest circuit is an improvement. Optocoupling for safety. There are two main reasons for using relays: a small control current can be used to switch a large load current, and the load is electrically isolated from the control circuit. This ‘electrical isolation’ refers to the fact that no current can flow from the load back to the control circuit. In other words, even if the load is connected to the mains it is still safe to touch the control circuit. In a mechanical relay, isolation is given by the fact that the relay coil is not connected to the relay contacts. When it comes to the more up-to-date elec- tronic version, this simple safety pre- caution is often omitted: the control circuit is connected direct to the triac and, with it, to the mains. In most applications, it is advisable to restore the isolation between the two parts of the circuit. Some way must be found to transmit the control signal to the triac without any actual electrical connection. The obvious transmission medium, nowadays, is light. If the control circuit is arranged to light an LED and a photo-transistor is used to trigger the triac, electrical isolation can be maintained. When LED and photo- transistor are mounted in one package, the complete unit is known as an opto-coupler. Synchronous or asynchronous? Switching the mains voltage can be done in several ways. At this point, our main interest is the difference be- tween synchronous and asynchronous switching. Synchronous switching refers to the fact that the load is turned on or off at the zero-crossing of the mains voltage (or current). This has the ad- vantage that interference pulses are reduced to a minimum. By now, every- one will have heard (or at least: heard of) the horrible radio and TV interferen- ce that inferior lighting dimmers can cause! Theoretically, synchronous switching has one draw-back: the load is not switched on or off immediately. The circuit must ‘wait’ for a zero-crossing. However, since zero-crossings occur every 1 0 milliseconds, it is rare indeed for this to be a problem. Nobody is going to worry about an aquarium heater being turned off 10 ms late! The only reason why synchronous switching has not become standard practice is that the control circuit it requires is more expensive . . . Circuit 1: simplicity itself. A simple, reliable circuit for a solid state relay is given in figure 1. In this circuit, the load is not turned on at the zero-crossing of the mains, but it is switched off in synchronism. As in virtually all triac circuits, synchronous turn-off comes free: the triac turns off when the current through it drops below a certain minimum value, the so- called hold current. The link to the timer/controller — or whatever other control circuit is used - consists of an opto-coupler. When sufficient current is passed through the LED, the photo-transistor will conduct. This, in turn, causes the ‘darlington transistor’ T1 to turn off, so that very little current can flow through the bridge circuit. (Note that two BC 107s in cascade can be used instead of Tl). In effect, the bridge circuit no longer forms a ‘short’ between points A and B, so that the voltage between these points can rise above the ‘zener’ voltage determined by D5 and D6. Depending — elektc 1979 switching mains-power on the phase of the mains voltage, one of these diodes will be forward-biassed (giving a ‘normal’ forward voltage drop of approximately 0.7 V) and the other will be reverse-biassed. No matter what the phase, the voltage across the two diodes will therefore be just over 6 V. The triac now receives gate current (via these two diodes, R2 and Cl), so it turns on - switching on the load. If the LED in the opto-coupler is not driven, the photo-transistor will turn off. As the voltage between points A and B rises after a zero-crossing of the mains, T1 will now turn on. This limits the voltage to two ‘diode drops’, two ‘base-emitter drops’ and the saturation voltage of T1 - about 3 V in all. Not enough to cause the zencr diodes to conduct, so no gate current flows to the triac. The load is switched off. In this circuit, the load is turned on when a current of 5 mA or more flows through the LED in the opto-coupler. The connection to the programmable timer/controller is shown in dotted lines: the anode is connected to the positive supply and the cathode to one of the four control outputs via a 470 n resistor. The resistor R and capacitor C, connec- ted across the triac, are especially important when switching inductive loads. The values depend on the type of load, as explained elsewhere (‘RC net- An improvement: synchronous switching As explained above, it is usually better to switch the load at the zero-crossing of the current through the triac. In this way, interference ‘spikes’ can be re- duced to a minimum. Turning off at the zero-crossing is no problem, as we have already seen: the triac takes care of this. Turning on is a different matter. Some way must be found to ensure that the triac is switched on when the voltage across it is zero - or ‘as near as makes no muchness’. To put it another way: the triac must not be turned on halfway through a (mains) period, when the voltage is nowhere near zero. The circuit shown in figure 2 takes care of this. In this case, the link to the control circuit is an opto-coupler consisting of an LED and a photo- thyristor. The gate current for the triac flows through R 1 , the diode bridge and this photo-thyristor; the thyristor is turned on when it is illuminated by the LED — provided its gate is not shorted by Tl. During most of the mains period, the voltage across the bridge circuit is sufficiently high to turn on Tl : the voltage has to be less than about 20 V for Tl to turn off. Only at this point - close to the zero-crossing — can the photo-thyristor be triggered, turning on the triac. On the other hand, once the thyristor is triggered Tl cannot turn on, so that gate drive to the triac will not be interrupted. When more than 10 mA is passed through the LED in the opto-coupler, the load will be switched on at the next zero-crossing. The connections to the programmable timer/controller are again shown in dotted lines; the values for the series connection of a resistor and a capacitor across the triac can be found from the separate explanation (see ‘RC network’). Continuous drive for small loads Both of the circuits described so far are reliable, provided the load is sufficient. One of the characteristics of triacs, however, is that they ‘extinguish’ Figure 1. A straightforward electronic relay. The load is not switched on during the zero- crossing of the mains waveform - except by sheer chance. Figure 2. An improved circuit that provides mains-synchronous switching. Figure 3. A rather more complicated circuit is required for switching small loads. Gate current for the triac is maintained during the whole 'on' cycle. Figure 4. A specially designed 1C, the TDA 1024, can also be used. Broadly speaking, this circuit does the same as that shown in figure 2. (cease to conduct) if the current passed ! through them falls below a certain value, known as the ‘hold current’. This is not always a disadvantage: in the two circuits described above it is this characteristic that ensures that the load is turned off at the zero-crossing of the current. It does, however, become a drawback when the load is so small that the load current is less than the hold current. Fortunately, a triac will always conduct if its gate current is sufficient - regardless of whether the main current is sufficient to ‘hold’ it. For small loads, therefore, the gate current must be maintained for as long as the triac is to remain ‘on’. This can be achieved as shown in figure 3, using two monostable multivibrators in a CMOS IC. The first monostable (MMV 1) provides 1 ms pulses at the positive-going zero-crossings of the mains waveform; the necessary trigger pulses are derived from the mains by means of R2, R3 and R4. Note that two resistors in series are used, so that only half the mains voltage is dropped across each - V* watt resistors cannot normally withstand more than about 250 V. For output pulses to be produced, the ‘reset’ input must be high; this is the case when supply (approximately 9 V) is used for the photo-transistor in the opto-coupler Tl; the supply to the CMOS IC and is conducting. photo-transistor is stabilised with a The output pulses from the first zener diode. monostable are used to trigger MMV 2. The transformer secondary voltage is This second monostable provides 35 ms not particularly critical. If it is signifi- output pulses - equal to almost twice cantly more than 6 V, however, the the period time of the mains waveform, values of R8 and RIO should be in- These pulses are used to turn on Tl, creased accordingly. Certain types of providing gate current to the triac so triacs may prove to require an excep- that the load is switched on. tionally high gate current or be satisfied When no current flows through the LED with an exceptionally low current, in in the opto-coupler, the photo-transistor which case the value of R8 can be will block, causing the reset input of modified. Nine times out of ten the MMV 1 to go ‘low’. No further pulses value given should be correct, will be produced, so that at the end of It should be noted that both the pri- the current 35 ms pulse Tl and the triac mary and the secondary side of the will cease to conduct, switching off the power supply are connected to the load. mains! Under no circumstances should The CMOS IC and transistor in this the same supply be used for another circuit require a low, positive supply circuit - the control circuit, for in- voltage. When the load is to be switched stance. The complete circuit shown on, gate current must be supplied must be seen as an isolated unit: the continuously (approximately 100 mA). only connections to the ‘outside world’ This effectively rules out the use of a are the mains and load connections and series resistor and diode to derive the the drive to the LED in the opto-coupler. supply voltage from the mains: some The connection to the programmable 20 W would dissipated in the resistor! timer/controller has already been de- For this reason, a small transformer and scribed ; the RC series-connection across bridge rectifier are used. The ‘raw’ the triac is discussed elsewhere. Finally: a special 1C A special integrated circuit for triac control is available from Philips; the TDA 1024. It was used in the ‘solid- state thermostat’ described in last year’s ‘summer circuits’ issue; a modified circuit for opto-coupler drive is given here (figure 4), When the photo-transistor in the opto- coupler is illuminated, the IC starts to produce mains-synchronous pulses to trigger the triac. The width of the pulses is determined by R4; with the value given, a pulse width of approximately 150 ms is obtained. When switching small loads (a 40 W lamp, say) it is advisable to increase the value of R4 to the maximum permissible (820 k) so that the pulse width becomes 650 ms. The gate current is equal to 6 V divided by the value of R6; approximately 90 mA with the value shown. Since the trigger pulses are quite short, the supply to the IC can be derived from the mains via a dropper resistor and capacitor (R5 and C3). The advantage of using a capacitor is that the phase shift leads to a much lower power dissipation. Constructional notes The most important thing to watch in this type of circuit is the electrical safety. Every part of the circuit, with the exception only of the connections to the LED in the opto-coupler, is connected to the mains. Careful con- struction is therefore a must. The choice of triac is determined mainly by the maximum load current. In some cases, switch-on surges can occur that are several times the nominal load current - particularly when switching motors, but to a lesser extent also if the load consists of incandescent lamps or heaters. The triac must obviously be rated accordingly. The same applies to the fuse, F; a ‘slo-blo’ type is preferable. Adequate cooling is required for the triac. Note that the heatsink will also be connected to the mains, unless a mica insulating washer is used. Where resistor ‘wattage ratings’ or capacitor working voltages are specified, these should be adhered to - of course. Capacitor C should also have a working voltage of at least 400 V. In all other cases, /» W resistors and ‘normal’ capaci- tors can be used. M The RC network In each of the circuits, an RC network is connected across the triac. This network is intended to prevent the triac turning on at the wrong moment, or even being damaged. Two things must be prevented in any triac circuit: an excessively high voltage across the triac and an excess- ively rapid increase in this voltage. Too high a voltage simply causes the triac to ‘break down'. Triacs are com- monly rated at 400 V, and 630 V types are also available. At first sight, 400 V seems an ample rating. However, when one considers that the peak voltage on a 245 V mains supply is approximately 346 V and that variations in the nom- inal supply voltage of ± 10% are quite possible, the safety margin becomes alarmingly small. The second point, an ‘excessively rapid increase in the voltage across the triac’, is perhaps less obvious. Most triacs can withstand a voltage increase at a rate of 200 volts per microsecond; a faster increase may cause the triac to turn on. One way to limit the rate of change would be to connect a Tat’ capacitor across the triac. However, if the triac is then triggered at a point where the capacitor is charged, the heavy surge current would almost certainly damage the triac. For this reason, a series resistor must be included. The minimum value can be calculated from the maxi- mum voltage and current rating; for a 6 amp triac, for instance: v max .-^« 56£2 also be estimated. If all resistances are taken together as R to t and the induct- ances are summed in the same way, the damping is given by: Since the whole idea is to damp out voltage spikes with a capacitor, it is logical to use a ‘fat’ one. In practice, 47n . . . 100n/400 V ... 630 V will nor- mally be used. The series inductance of mains wiring and load can be estimated as 100 mH in most applications (barring truly inductive loads). If the load consists of, say, a 60 W lamp (with a resistance of 1 k) and a 56 £2 resistor is used for R, the damping will be: d = - s 11*7 A further point to watch is the effect of an (even partly) inductive load. The RC network across the triac and the RL network formed by the load together represent a series RLC circuit. If this resonant circuit is insufficiently damped (damping d< 1) oscillation can occur - with the triac switching on and off at a frequency determined by the RLC network. At the same time, the voltage can swing up to above the maximum rating of the triac . . . When selecting the resistance value, therefore, the damping in the resonant circuit must The result? Oscillation, and the lamp will refuse to go out. The obvious remedy is to increase the value of R ; the minimum value (for d=l) can be calculated as follows: dV_ 10* 10 3 -346 _ «10k. Adequate. No problems are to be expected until the load resistance becomes less than about 36 £2 (equiv- alent to a good 1600 W). If loads in excess of this are to be switched, a larger capacitor value will be required. The maximum rate of voltage increase occurs if the triac is triggered at the peak of the mains voltage. In the example given, it is equal to: This is just within the safe limit. The problems associated with inductive loads can be illustrated with a simple example. Let us assume that a fluor- escent lamp with its associated ballast is to be switched. Common values for the resistance and inductance of the ballast are 200 £2 and 1 H, respectively. The damping is therefore approximately . _ 250 For ‘normal’ loads (incandescent lamps, heating elements etc.) up to 1 kW, a 6 A triac can be used. In this case, a safe value for R is 56 £2/ 1 W and a good capacitor value is 47 n/400 V, There is no harm in playing it safe: the capaci- tor value can be increased to 100 n and the working voltage to 630 V if desired. For 10 A triacs (loads up to 1600 W), the resistance value can be decreased to 39 £2, provided a 100 n capacitor is used. The same values can be used for 15 A triacs; 27 £2 and 150 n or 220 n are also permissible in this case. When switching fluorescent lamps (note that ‘dimming’ is not possible with these circuits!) the value of R will have to be increased considerably - to over 10 k. If other ‘odd’ loads are to be switched, the corresponding values for R and C can be calculated as described above. random doorbell elektor i 1979 - 5-17 random (A Houghton) tune doorbell The circuit diagram of the ‘random tune’ doorbell is shown in figure 1. As can be seen, it basically consists of two squarewave generators, a counter, and a current controlled oscillator. The fre- quency of the first squarewave genera- tor (N1/N2) can be varied between ap- prox. 12 and 900 Hz, whilst that of the second generator (N3/N4) is roughly 1 kHz. The counter, IC3, is enabled when the clock enable input is taken low. However due to the integrating effect of C3/R4, the negative going edge of the first squarewave enables the counter for only a brief period. The count is only incremented when a positive going edge from N3/N4 coincides with a negative pulse from N1/N2. The doorbell thus functions as follows: When the pushbutton switch SI is in the open position, pin 15 (reset) of IC3 is high and the counter is inhibited. If SI is pressed, then the first time that a clock enable- and clock pulse coincide, the counter will increment to ‘1’. The counter will remain in this state until a clock pulse again coincides with a clock enable pulse, whereupon the counter is once more incremented. Thus each of the counter outputs is taken high in The outputs are commoned via resistors R6 ... R13 and fed via P2 to the current controlled oscillator T1/T2. Thus the value of whichever output resistor is high, together with the setting of P2, determine the pitch of the oscillator sig- nal. The result is a semi-random tune, in which the length of each note is depen- dent upon the length of time between clock-enable and clock pulses coin- ciding. In order to introduce a pause between successive cycles of the counter, output 0 of the counter is left floating. Simi- larly, by leaving output 5 (pin 1) uncon- nected, each ‘phrase’ will consist of two groups of four notes, separated by a rest. Thus the ‘tune’ will always have a certain basic ‘shape’, regardless of varia- tions in the length of successive notes. In order to eliminate the possibility of the two squarewave generators influ- encing one another, i.e. tending to syn- chronise, it is advisable to use separate 401 l’s for each. M 5-18 - elektor may 1979 delay lines (2) delay lines (2) Having dealt with reverberation and echo in a previous article (see Elektor 46, February 1979) we now take a look at how delay lines can be used to achieve a wide variety of interesting special effects such as double tracking, vibrato, phasing, chorus etc. Such applications are of particular inter- est to the amateur musician since they can be implemented using relatively short delay lines and hence at comparatively low cost. The article is rounded off with a look at the contribution of delay lines to studio recording tech- niques and sound reinforcement systems. Unlike reverberation and echo, such effects as vibrato, phasing, flanging, chorus and string ensemble can be ob- tained using comparatively short delay lines. In practice, a single bucket-brigade memory is often all that is required. As we shall see, most of the effects men- tioned above are achieved by varying the frequency at which the audio signal is clocked through the delay line, however there is one commonly used technique where this is not the case. Automatic Double Tracking (ADT) The block diagram of figure 1 illustrates the simplest application of a short delay line, in which the audio signal is delayed by approx. 1 to 5 ms and then summed with the direct signal. The result is that a solo voice or instrument is made to sound ‘fuller’ or stronger, since the human ear is unable to distinguish between the original and delayed signals and has the subjective impression of increased volume. The actual increase in signal amplitude, however, is consider- ably smaller than the perceived increase in volume (which can be anything up to 6 dB); thus there is no danger of equip- ment overload on signal peaks. If several double tracking elements are connected in cascade, a multiple voice effect is obtained, this being the first step towards ‘chorus’. Chorus True chorus effect is obtained when the delay time is not constant, but is subject to small variations. In the case of both digital delay lines and analogue ‘bucket-brigade’ memories the delay time is determined by the clock fre- quency and by the length of the delay line. Thus the delay time can be varied by using a voltage controlled oscillator as clock generator, which is modulated by a low frequency random voltage generator (see figure 2a). In practice more than one delay line is used. The circuit shown in figure 2b consists of 4 delay lines, each of which is indepen- dently varied by a random clock signal. The principle of chorus generation is to simulate the effect of a multiplicity of I sound sources — as are present in a I voice or string section of an orchestra. Although a group of instruments may be required to play the same note, due to variations in the phase relationship of each sound the human ear perceives that several instruments are present. These phase discrepancies are caused by slight differences in the mechanical construc- tion of similar instruments, differences in the musicians’ technique and in the different path lengths which the sounds must travel to the listener or recording microphone. Thus randomly varying the length of the delay lines ensures that the phase relationship of the output signals is constantly changing, thereby producing a multiple image effect. For simulation of complex orchestral sounds, in particular those of stringed instruments, the arrangement of figure 2c is used. The modulation signals of the clock generators (VCOs) are periodic, not random, and are locked out-of-phase with one another. The result is that whilst the delay time of one line will be increasing, the delay time of another will be decreasing, and vice-versa. As the length of the delay lines are varied, so is the phase relation- ship of the signals at the output. A second ‘fast’ modulation signal superim- posed on the clock frequencies has the effect of further enhancing the pattern of phase differences and produces a rich, heavily textured sound composed of an apparent multiplicity of separate instruments. Vibrato and Phasing If a periodic clock frequency signal is used instead of a random clock signal, vibrato and phasing can be obtained. Figure 3a shows a basic circuit for vi- brato, whilst 3 b illustrates how phasing can be achieved. As can be seen the basic difference in the two circuits is that the vibrato signal is taken directly from the output of the delay line, whilst in the case of phasing, the de- layed and direct signals are summed. Vibrato essentially involves alternately speeding up and slowing down the sampled signal as it progresses through the delay line. Since the rate at which the signal enters the delay line is dif- ferent from that at which it exists, the result is variations in the pitch of the Figure 1. Basic principle of ADT - automatic double tracking. A very slightly delayed version of the audio signal is summed with the original. The result is that the signal is inten- sified, without a significant increase in signal amplitude. Figure 1b shows a practical circuit for such an arrangement. Figure 2a. Block diagram of a basic chorus generator. By randomly varying the clock frequency of the delay line the changing phase relationships between the direct and delayed signals produces the effect of a multiple sound source similar to that of a voice choir. Figure 2b. In practice more than one delay line is normally used. In the circuit shown here, there are four delay lines, the clock frequencies (f c 1 .... f c 4) of which are independently varied by separate random voltages. Figure 2c. For string ensemble effects a multiple phasing unit of the type shown here is used. The principle involved is similar to that of the circuit in figure 2b, however in contrast to the above circuit the clock fre- quencies of the delay lines are modulated by periodic (not random) signals. In fact two modulators are used, one 'fast' and one ‘slow', and the modulation signals to each VCO are held in a fixed out-of-phase relationship. When the outputs of the delay lines are summed, the periodic variations in the delay time of each line lead to highly complex phase patterns which lend the resultant sound a rich, vibrant quality characteristic of a string j 5-20 — elektor may 1979 delay lines (21 signal, i.e. frequency modulation. Rela- tively short delay times are used (approx. 5 ms), which means that high clock frequencies are possible and hence input signals with a wide bandwidth can be processed in this way. The modulation rate is normally in the region 5 to 10 Hz. The modulation depth (i.e. the extent to which the signal frequency is shifted up or down) of the vibrato signal is determined by the average delay time of the delay line, the modulation depth of the clock signal and the rate of modulation (vibrato frequency). Thus with a delay time of e.g. 5 ms, a variation in clock frequency of ± 5% about an average value, and a vibrato frequency of 10 Hz, the signal frequency will vary by ± 3.14%. As a comparison, the musical interval of one semitone corresponds to a frequency change of just under 6%. Phasing is an effect which is extremely popular with many musicians, and one which is very difficult to describe! Many people liken it to the effect of passing the sound through a long tunnel, or describe it as a ‘wooshing’ effect, the music seeming to ‘breathe’ in and out in a regular rhythm. This highly individual sound is obtained by summing the direct and delayed signals. At frequencies where the delay is equal to an odd number of half periods of the signal frequency the direct and delayed signals will be 180° out of phase and therefore cancel. Conversely, at frequencies where the delay time is equal to an even number of half periods, the two signals will be in phase and reinforce. The result is a series of attenuation notches in the response of the signal at the odd har- monics of the fundamental. The process is the equivalent of passing the audio signal through a comb filter. The distance between successive notches is inversely proportional to the delay time, and is in fact equal to—, where t is the delay time. Thus with r = 10 ms, the frequency response of the output signal will exhibit a notch every 100 Hz. By cyclically varying the delay time (by low frequency modulating the clock oscil- lator) the distance between successive peaks in the response is also varied (see figure 4), and it is this which produces the characteristic phasing effect. Delay times for phasing are normally between approx. 1 and 20 ms, whilst the modula- tion signal from the low frequency oscillator is generally a sinewave or triangle, with a frequency between roughly 0.05 Hz (i.e. one complete cycle every 20 seconds) and 1 Hz. Frequency Modulator for Chorus, Phasing and Vibrato Figures 5a and 5 b show the block dia- gram and circuit diagram respectively of Figure 3. Basic circuit arrangement for phasing (3a) and vibrato (3b). In both cases the clock frequency of the delay line is modulated by a low frequency oscillator. The difference between the two effects is that for phasing, the delayed and direct signals are summed. The result of the shifts in phase between these signals is that the response of the sum signal exhibits a series of attenuation notches which are swept up and down the audio spectrum. The vibrato signal consists simply of the output of the delay line. The variations in phase of the delayed signal amount to frequency modulation, i.e. the pitch of the signal is periodically varied about a centre frequency. Figure 4. Varying the clock frequency of the delay line has the effect of varying the distance between successive attenuation notches in the signal's response. It is this which produces the characteristic phasing effect. Figure 5a. Block diagram of a frequency modulator which can be used as the basis for a special effects unit providing phasing, vibrato, chorus, ADT etc. Figure 5b. Circuit diagram of a frequency modulator using the TDA 1022. The circuit is based on a manufacturer's application note (Mullard). Figure 5c. Circuit of a suitable lowpass input filter for use with delay lines. The turnover frequency of the filter is 15 kHz and the filter roll-off is 24 dB per octave. a frequency modulator using the TDA 1022 bucket-brigade memory. This circuit forms the basis of an audio effects unit for chorus, phasing and vibrato. A simple VCO built round two BC 337 (or BC 107) transistors provides the clock signal, whose frequency can be modulated by means of a separate sinewave oscillator. The frequency of this vibrato oscillator can be varied between 0.5 and 7 Hz by means of a 1 00 k potentiometer. The modulation signal is fed to the VCO via an emitter follower, whose emitter resistor is formed by a potentiometer (intensity) thus allowing the modulation depth to be varied. A random voltage circuit is included in order to provide aperiodic phasing/vi- brato (chorus effects). The random voltage is derived by amplifying and low pass filtering the noise voltage of a 13 V zener diode (more commonly available 12 or 13 V, 0.4 W zeners can also be used). When switched into circuit, the random voltage controls the vibrato oscillator, which in turn controls the VCO. The intensity of the random voltage modulation can also be varied by means of a potentiometer (random intensity). Figure 5c shows the circuit of a suitable lowpass filter to limit the bandwidth of the audio input signal. As was explained in the first part of the article, since the clock frequency must be at least twice the maximum signal frequency, there is a trade-off between delay time (which of course is determined by clock fre- quency) and signal bandwidth. The filter shown here has a turnover fre- quency of 15 kHz and a filter slope of 24 dB per octave. The circuit of an audio effects unit for phasing, vibrato and chorus using the above frequency modulator is shown in figure 5d. Potentiometers PI and P2 determine the relative proportions of direct and delayed signal mixed at the output. If the delayed signal only is fed to the output, vibrato is obtained. As a rule fairly fast vibrato, i.e. a modula- tion frequency of several Hertz, is best, whilst the modulation depth (clock fre- quency deviation) should be kept low. If the direct and delayed signals are mixed, either chorus or phasing is the result, depending on whether a random or periodic modulation signal is used. A gradual transition from vibrato to phasing can be obtained by slowly increasing the amount of direct signal summed with the delayed version. The above circuit can also be used for ADT. With the vibrato intensity turned right down a constant delay time of approx. 3.2 ms is obtained. Mixing direct and delayed signal will then produce the double tracking effect. Stereo phasing For multi-channel effects, the add-on 5-22 - elektor may 1979 5d A1.A2.A3 - 54 TL 084 circuit of figure 6 provides three separ- ate output signals. Output I gives the sum of the delayed and direct signals, at output II is the direct signal minus the delayed signal, whilst at output III is the delayed signal minus the direct signal. Stereo phasing, chorus and ADT are ob- tained by taking either outputs I and II or I and III as the stereo signal pair. In case of vibrato, obviously all three out- puts will give the vibrato signal, with output II being inverted with respect to outputs I and III. Any of the three outputs can in principle be used to provide a mono signal, however it is normal to use the sum signal at output I. Sound reinforcement systems and studio work With the aid of delay lines it is possible to exploit two interesting psycho- acoustic phenomena related to the time taken for sound waves to travel through free air. The Haas effect and the law of the first wavefront According to the theory of Dr Haas, a blindfold listener will determine the source of a sound not by amplitude, but on a ‘first arrival basis’ . If for example the same signal is fed to two loudspeakers of a stereo system, delaying the signal to the left channel speaker by several milliseconds will give the listener the impression that the music is originating almost entirely from the right channel speaker. Even if the volume of the left channel signal is increased to several times that of the right channel, the listener will continue to be deluded into thinking the sound is coming exclusively from the right- hand speaker. The increase in left channel volume only affects the listener’s impression of overall loudness of the signal; it has little or no effect on the perceived direction. The use of electronic delay lines allows the sound technician to focus the listener’s attention on a particular sound source by ensuring that the other signals are delayed. When recording orchestral music delay lines are often used to counteract the effect of different path lengths between individual instruments and the microphones. Thus when recording a large orchestra using one main stereo microphone (for good transparency and resolution) supported by a series of secondary microphones to pick up instruments further removed from the main microphone (e.g. second violins), the latter tends to pick up the sound of distant instruments after the more closely positioned microphone. Due to the Haas effect this can lead to falsification of the desired stereo image, a problem which is only partially resolved by lowering the level of the secondary microphone. The ideal solution is to employ delay lines to equalise the path lengths. A similar technique can be used when recording an orchestra with a main microphone close to the body of the orchestra and one or more secondary microphones positioned further back in the hall to capture reverberation. At distances of greater than 15 m between main and secondary microphones, the time taken for signals to reach the two can differ by more than 50 ms. Path length differences of this order can produce intrusive echoes. By employing delay lines the main microphone signal can be held back to reduce the period between direct and reverberation signals to acceptable levels. In the case of P. A. systems used in large halls or in the open air, excessive path Figure 5d. Block diagram of a complete audio effects unit. In addition to input and output lowpass filters and the frequency modulator of figure 5b, the circuit includes an input amplifier with variable sensitivity (A1), a buffer amplifier (A2), and an output mixer (PI, P2, A3), which allows the direct and delayed signals to be summed in any desired proportion. The relative propor- tions of the two signals determine the tonal character of the resultant sound. Figure 6. Stereo effects can be obtained by extending the output mixer circuit to provide two difference outputs. Figure 7a. Illustration of how a variable speech processor expands or compresses the time domain of a signal, allowing it to be reproduced at other than normal speeds without altering the pitch of the signal. Figure 7b. Block diagram of a variable speech processor. i delay lines ( 2 ) elektof may 1979 — 5-23 ■A A/VWVWV 1 miwmh — * w\AA ) : ^ — i f VW\/ • — - “AAaAaAAAA/ length differences between signals from different loudspeakers can also cause the intelligibility of the speech signal to be impaired. Here again delay lines can be used with advantage to reduce the interval between direct and reverberation signals reaching the listener to below the crucial 50 ms mark. The ideal interval between successive signals is in the region of 20 ms, since the effect is then similar to that of double tracking, i.e. the listener ‘integrates’ the two sounds and subjectively experiences a slight increase in the volume of the signal. In the case of loudspeaker installations which do not incorporate delay lines, the first signal to reach the listener will be that from the loudspeaker closest to him, which normally will not be situ- ated in the line of sight between himself and the person speaking into the micro- phone. Thus, due to the first wavefront principle, he will see the speaker in front of him, but will hear him from the side, a phenomenon which can often have a slightly disconcerting effect. The problem can be overcome by using a small loudspeaker at the front of the stage or hall to reproduce the direct signal, and delaying the signal to the remainder of the loudspeakers suf- ficiently to ensure that their signals reach the audience after the signal from the front loudspeaker. If a suitable delay time is used the output of the front loudspeaker can be considerably smaller than that of the others. Once again, with a delay of approx 20 ms between successive signals the listener perceives them as simultaneous and the intelligibility of the speech signal is improved. Variable Speech Control, Level Control and Anti-Click Units Variable speech control is a process which allows recorded speech to be replayed at faster or slower speeds, without affecting the pitch of the signal. As every owner of a variable speed tape recorder knows, playing back a re- cording at a higher than normal speed produces a high-pitched twittering sound, whilst lower speeds give an incromprehensible deep grumbing noise. Variable speech control prevents these changes in voice pitch. Signal 1 in figure 7a shows 9 cycles of a 200 Hz sinewave recorded at normal speed. When replayed at twice the recording speed the signal frequency is doubled to 400 Hz (signal II). Variable speech control ‘stretches’ the first four cycles of signal II to twice their ‘length’ i.e. the time domain of the signal is compressed. The result is signal III, which has the original frequency of 200 Hz. Cycles 5 ... 8 of signal II (shown dotted) are suppressed. The informational content of these 4 cycles is in fact superfluous, wich means that the intelligibility of a speech signal is unaffected by replay at twice the original speed. When replaying at half the original speed the opposite occurs. The original 5-24 — elektor may 1979 delay lines (2) capitals from the ASCII keyboard 8 Qo-t-i ► detector ' 790«SB signal is slowed down to a frequency of 100 Hz (signal IV). The section of signal containing the first four cycles is compressed into half its original period (signal V), the resulting ‘hole’ or time gap is filled by repeating the first four cycles, which have been specially stored for this purpose (signal VI). Since the pitch and speech rhythms (at half their normal speed) of the original signal are preserved, the extra informa- tion is not important. In practice the speech signal is processed by feeding it through a bucket brigade memory and continuously varying the clock frequency. A simplified block diagram of a variable speech processor is shown in figure 7b. A sawtooth gener- ator, the frequency of which is deter- mined by the speed of the tape recorder, is used to modulate the clock generator of the delay line. In the case of faster than normal playback the sawtooth ramps negative. During each period of the sawtooth the clock frequency is continuously varied from a maximum to a minimum value. The lower the clock frequency, the longer each suc- cessive sample takes to travel through the delay line. The result is that the time domain of the output signal is extended (its frequency is reduced), whilst leaving the shape of the wave- form unaffected. Since all the frequency components of the original signal were ‘slowed’ by the same relative proportion, the harmonic structure and therefore the tonal character of the signal are preserved. In the case of speech expansion (the time domain of the speech signal is expanded by playback at a slower than normal speed) the opposite occurs. The sawtooth ramps positive and the clock frequency varies from an initial minimum to a maximum value, with the result that the pitch of the signal is increased. The variable speech processor can also be used to falsify the pitch of signals played at their correct speed, i.e. real- time pitch shifting. Thus by expanding the time domain of the speech signal the effect is of increasing its frequency and pitch, a trick which can be used for cartoon voices etc. Conversely, by compressing the time domain of the speech signal its frequency can be low- ered. This technique is useful in un- Figure 8. Basic principle of a level control circuit incorporating a delay line. The detector monitors the input signal for overloads, and as soon as a signal peak is detected, activates the limiter circuit. The delay line ensures that the gain reduction occurs before the input signal reaches the limiter, thereby preventing initial transient distortion. The same principle can be used for click suppressors etc. scrambling the voice signals of divers working in helium-filled atmospheres. Finally, two closely- related applications of delay lines in specialised studio equipment: level control units and click eliminators. In both cases the principle involved is the same, an audio signal is monitored for a particular irregularity. In one case it is signals above a preset maximum level, and in the other case a particular type of noise or distortion (clicks or pops caused by scratches, old recordings etc). Delay lines are used to give the control circuits sufficient time to respond to signal overloads or noise transients. The basic arrangement is illustrated by the block diagram of figure 8. The input signal is fed to a delay line and to a detector circuit which controls the limiter or noise suppression circuit. Since the signal fed to the detector circuit is undelayed in the case of e.g. a signal overload, gain reduction sufficient to prevent overshoot will have occurred before the delayed signal (and signal peak) arrive at the limiter. Due to the reduction in the cost of bucket brigade memories, click suppressors are now a feasible proposition for the amateur, who can make more or less noise-free recordings of old records which pre- viously were ‘unlistenable-to’. H CAPITALS from the ASCII keyboard BASIC made easy The ASCII keyboard (Elektor, November 1978) is more versatile than may appear at first sight. Some readers have com- mented that a ‘shift-lock’ would be useful, particularly when it is used for programming in BASIC. In actual fact, we can go one stage further: an ‘upper- case lock’! In the ASCII code, capitals and lower- case letters are distinguished by the value of the sixth bit (S6 on the charac- ter generator). For capitals, this bit is logic ‘0’; for lower-case letters it is logic ‘1’ (see table 1 in the original article). The character generator used, the AY-5-2376, not only provides the usual 7-bit ASCII code: it has an eighth output (S8). Although this is not made clear in the data sheet, S8 can be used instead of S6. The result is all that could be desired: the shift key operates normally for numerals, punctuation marks etc. — but only CAPITALS are printed when a letter key is operated ! This facility can be extremely useful for instance, when programming in NIBL. The ‘shift’ key need only be used when special symbols are required; it is no longer required for printing text. A single-pole change-over switch can be added as shown in the figure. H (Keyboard) S8 S6 KB5 (Elekterminal) interface for uPs 1979 - 5-25 interface for jiPs The specifications for a serial interface between computer and terminal are given by the so-called RS232C and V 24 standards — among others. Although these standards are in widespread use, this is not to say that all (micro-) computers include the correspond- ing interface. Only a few components are required for a 'standard' interface. The circuit described in this article can be used in conjunction with both the Elektor SC/MP system and the popular KIM 1. Figure 1. Interface for the SC/MP system. The input side is given in figure la, and the output in figure 1b. The main difference between computer- and RS 232C/V24 signals is the defini- tion of the signal levels. Within a com- puter system it is common practice to use TTL levels, with logic ‘0’ correspon- ding to 0 V and logic ‘1’ to +5 V. The interface standards are rather different: logic ‘0’ may be anything between +5 V and +25 V, and logic ‘1’ is ‘defined’ as between -5 V and -25 V. Note the level inversion: positive voltages for logic ‘0’ and negative voltages for logic ‘1’! The supply voltages in the SC/MP system are +5 V and - 1 2 V, so it is ‘logical’ to use these levels for ‘0 and ‘1’ respectively. No negative supply voltage is available in the KIM 1 system, so an additional power supply must be added (giving a voltage between —5 V and -25 V). Two positive voltages are present (+5 V and + 12 V). Either of these could be used for the positive logic level, but the higher voltage is to be preferred since it gives better noise immunity. The only disadvantage is that the power dissipa- tion is higher in this case. SC/MP interface The input/output software for the SC/MP normally uses the sense B input and flag 0 output for serial data transfer. A suitable interface for these connec- tions is shown in figure 1 . The input interface (figure la) consists interface for uPs 5-26 - elektor may 1 979 Figure 2. Modified communication interface for the KIM 1 microcomputer. Input and output sections are given in figures 2a and 2b. respectively; the relevant sections of the KIM circuit are also shown. Figure 3. Multi-purpose printed circuit board for the communication interface (EPS79101). The track layout is given in figure 3a; figure 3b is the component layout for use with the Elektor SC/MP system and figure 3c is for use with the KIM. 2b of four components. A diode (Dl) and resistor (R2) limit the input signal, after which the transistor performs the conversion to TTL levels. Resistor R3 is not required if the input signal conforms to the official standards. However, the interface can also be fed from an opto- coupler or open-collector gate; in either of these cases R3 can be used as pull-up resistor. The output side of the interface is slightly more complicated. The TTL levels from the SC/MP must be conver- ted to +5 V and -12 V. A low output impedance is a must, since lines of up to 10 m (30’) are quite common. Futhermore, the circuit must be short- circuit proof. Figure lb gives the circuit. A current source (T3) is used to obtain the low output impedance; it has the added virtue of being short-circuit proof. A second transistor (T2) is included as an inverter, to obtain the correct logic level relationship between the flag 0 output and the interface output. Resis- tor R5 is not strictly necessary: it improves the switching characteristic of the interface, giving sharper edges. The second output, via diode D4, can be used to drive the LED in an opto- coupler. The output current will have to be reduced in that application, by increasing the value of R7 to 15 f2. The same circuit can also be used for buffering the flag f> output, without altering the levels. In that case R8 should be connected to supply common instead of negative supply. The printed circuit board (figure 3) is designed to cater for all possible applications. KIM interface Only a few modifications are required if the interface is to be used in conjunc- tion with the KIM 1 . The TTY (teletype) interface in the KIM system will also have to be modified slightly. The serial data input is no problem: the same circuit can be used. The only difference is that the value of R1 (in figure la) must be reduced to 470 to cope with the heavier load require- ment. The circuit is therefore as shown in figure 2a; it can be connected to the KIM’s ‘application connector’ as shown. For the serial output, some minor surgery on the KIM board is required. The TTY output on the KIM is intended for teletypes with a so-called current loop, but if it is to be used with the interface described here the polarity of the signal after the output gate must be inverted. Transistor T2 on the interface board is used for this, as shown in figure 2b. The track between PB0 (pin 25 of U2) and pin 9 of U26 on the KIM board must be broken, after which T2 can be wired in series as shown. The signal at output A-U on the application connector now has the correct polarity to drive the current source (T3 on the interface board). The printed circuit board | All the options described, both for interface for uPs elektor may 1979 — 5-27 Table 1 Parti lilt MEMORY-DUMP ROUTINE BY D. HENDRIKSEN 0C00 C4 0C 35 C4 00 31 C4 0C 37 C4 86 33 C4 0C 36 C4 0C10 95 32 C4 0D CB FD C4 0D 3E 8F 80 C4 0A 3E C4 20 0C20 3E 35 01 40 35 40 1C 1C 1C 1C 01 C3 80 3E 35 01 0C30 40 35 40 D4 0F 01 C3 80 3E 31 01 40 31 40 1C 1C 0C40 1C 1C 01 C3 80 3E 31 01 40 31 40 D4 0F 01 C3 80 0C50 3E C4 20 3E C4 10 CB FE C4 20 3E Cl 00 1C 1C 1C 0C60 1C 01 C3 80 3E C5 01 D4 0F 01 C3 80 3E BB FE 9C 0C70 E5 BB FD 9C Al C4 0C CB FF 08 08 08 BB FF 9C F9 0C80 00 90 8F 05 0C 00 30 31 32 33 34 35 36 37 38 39 0C90 41 42 43 44 45 46 01 C4 64 8F 06 06 DC 01 07 C4 0CA0 09 C8 20 C4 F0 8F 02 B8 1A 98 10 40 D4 01 C8 14 0CB0 01 1C 01 06 DC 01 E0 0C 07 90 E8 06 D4 FE 07 3E 0CC0 90 D4 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Resistors: R1 = 4k7 (470 n ) R2 = 4k7 R3 = 4k7* R4= 10 k R5= 1 k* (1 k) R6 = 1 k R7 = 6fl8 or 15 «* R8 = 270 n/1 W Semiconductors: T1,T2= BC107B, BC547Boreq. T3= BC177B. BC557B or eq. D1 . . . D3 = DUS D4 = DUS* Where values for SC/MP and KIM differ, the values for the KIM are given in brackets. SC/MP and KIM systems, can be moun- ted on the p.c. board shown in figure 3. The component layout for use with the SC/MP system is given in figure 3b; figure 3c corresponds to use in a KIM system. A so-called modem connector can be used, if required. The mounting holes for the connector correspond to those of the p.c. board, so that the complete unit can then be mounted with only two bolts. The only thing to watch, in this case, is that the components must be mounted as nearly flush with the board as possible — there will not be much room between the board and the panel on which it is mounted! An alternative is to use a right-angle modem connector, so that the board can be mounted horizontally. Software The monitor program for the KIM 1 already includes a teletype routine. The selection between a hexadecimal keyboard or teletype input is made by a wire link on the ‘application connec- tor’. In this case, since the TTY input is required (even if it is actually used for the Elekterminal), the wire link (or a switch) between pins A-V and A-21 on the connector must be included. In the Elektor SC/MP system, no pro- vision was made for connecting a teletype. However, only small programs will be required to obtain the necessary functions. As an example, a memory- dump routine is given in table 1. By means of this program, the memory contents will be printed out in hexa- decimal - starting at a specified address. The length of the block is determined by the number of lines specified for the print-out. When the complete block has been ‘dumped’ the processor goes to the ‘HALT’ mode; operating the HALT- reset key causes a further block to be printed out, etc. The ‘modify’ routine is used to enter the new start address in memory locations 0C01 (upper address byte) and 0C04 (lower address byte). In the same way, the desired block length can be stored in location 003. The program itself is started at 0C00. The program listing given in table 1 was actually printed using this memory- dump routine, as can be seen from the three underlined data bytes. The transmission rate is 300 band. H 5-28 — elektor may 1979 sweep generator sweep generator Determining the frequency response of an amplifier normally requires a series of carefully conducted test measurements, a large supply of graph paper, and plenty of patience. Wrestling with peak-peak values, RMS voltages, dBs, logarithms etc. can prove to be something of a chore, and it is all too easy to make mistakes which 'distort' the final results. However if one possesses an oscilloscope, there is a way of displaying frequency response curves directly upon its screen — provided one also has the instrument described here, namely a sweep generator. (L. Koppen) Sweep generators are not usually part of the basic equipment of amateur elec- tronics enthusiasts, for the simple rea- son that such an instrument is normally too expensive. However if we are con- tent with an instrument which will pro- vide relative results (which is often more important than the measurement of a quantity with absolute accuracy), then there is no reason why a sweep genera- tor should not be included in the test equipment of every hobbyist. Why sweep? What exactly is a sweep generator? The simplest way to answer this question is to look at how one would normally set about measuring the frequency response of an amplifier. The usual measurement set-up is illustrated in figure 1 . The amplifier under test is provided with an input signal from a low fre- quency sinewave generator. The ampli- tude of the amplifier output signal is measured on an AC voltmeter. We now ensure that the amplitude of the input signal is held constant, and measure the amplitude of the output signal for a number of different input frequencies. The results are plotted on graph paper, with frequency along the horizontal axis and amplitude (voltage) along the verti- cal axis. In this way the frequency re- sponse of the amplifier is immediately apparent - how flat it is, at what fre- quency it starts to roll off, etc. With this arrangement, each time we wish to make a new measurement the frequency of the sinewave generator must be increased by hand. It would of course be much simpler if, in some way, this could be done automatically. This would also allow a continuous increase of the frequency (instead of in discrete steps), thereby ensuring that we are not jumping over small dips or peaks in the response. Thus what is required is a sig- nal whose frequency increases continu- ously. In other words, a sweep genera- tor. Figure 2 illustrates how a sweep genera- tor is used to display the frequency re- sponse of an amplifier on an oscillo- scope. The sweep generator actually provides two signals: the above described input signal for the amplifier, and a voltage which varies with the frequency of the input signal. The latter signal, desig- nated X, is used to control the horizon- tal deflection of the oscilloscope (X am- plifier). The vertical deflection of the spot is determined by a voltage which is proportional to the amplitude of the amplifier output signal. This is obtained simply by rectifying and smoothing the amplifier output signal. The result of such an arrangement is that the fre- quency response of the amplifier is dis- played directly on the scope screen, with amplitude along the vertical axis, and frequency along the horizontal axis. Not linear, but logarithmic As most readers will no doubt know, it is generally the case that a logarithmic scale is used for the frequency axis in such graphs. The question is, how to en- sure a logarithmic relationship between the frequency of the sweep generator signal and the external timebase input signal (X). One answer is to increase the frequency of the sweep signal linearly, whilst that of the X signal is increased logarithmically. However a better solu- tion is to let the X voltage increase linearly, and increase the frequency ex- ponentially (with time). In this way there is a logarithmic relationship be- tween frequency and X voltage, whilst the horizontal deflection of the scope will remain constant. This means that the brightness of the trace will also re- main constant, and more importantly, affords the possibility of using the (lin- ear) timebase generator of the scope (as not every scope has an X-input). It should be noted that the vertical axis of the response ought to have a logarith- mic scale as well, a facility which is not provided by the circuit described here. Strictly speaking, however, the pro- vision of a logarithmic Y axis is not among the functions of a sweep genera- tor; its job is simply to provide the ne- cessary input signals for the measure- ment procedure. A suitable circuit (with p.c. board) was published in Elektor, January 1978: the peak programme meter. Basic circuit The basic design of the sweep generator is illustrated by the block diagram of figure 3. sweep generator elektor may 1979 - 5-29 An asymmetrical squarewave oscillator is used to trigger a sawtooth generator, which provides the control voltage for the X input of the scope. The X-voltage is also used, via an exponential con- verter, to control a VCO, resulting in a signal with a frequency exponentially related to the X-voltage. The block dia- gram is completed by buffers for the various output signals. The sweep generator has two outputs, the first offers a choice of sinewave or triangle waveforms, whilst the second provides a squarewave. Although tri- angle and squarewave signals are not generally employed to determine the frequency response of circuits, they are useful in a number of other applica- tions. The circuit also contains a ‘manual’ switch, which allows the frequency of the generator to be continuously varied by means of a potentiometer, rather than automatically swept up and down the frequency range. The circuit in detail The complete circuit diagram of the sweep generator is shown in figure 4. As can be seen, the circuit contains a num- ber of switches which function as fol- lows: 51 - sweep inhibit 52 - sweep/manual 53 — sinewave/triangle 54 — frequency range 55 - output attenuator A more detailed description of these functions will be dealt with later in the text. An asymmetrical squarewave oscillator is formed by the circuit round T1 and T2. The output of this oscillator is at- tenuated by R6 and R7 then limited by diodes D1 and D2 which are connected in ‘reverse-parallel’ . This signal is then used to trigger the sawtooth generator Figure 1. This figure illustrates the basic set up for measuring the frequency response of an amplifier, using a low frequency generator and an AC voltmeter. Figure 2. With the aid of a sweep generator and an oscilloscope the same measurement can be carried out virtually automatically. The sweep generator provides a sinewave out- put signal, the frequency of which increases continuously, and a sawtooth signal which is used as an external timebase input for the Figure 3. Block diagram of the sweep genera- tor. In order to provide a logarithmic fre- quency scale, the circuit ensures an exponen- tial relationship between the instantaneous value of the sawtooth and the VCO fre- 5-30 - elektor mav 1979 sweep generator consisting of IC1 and the unijunction transistor (UJT) T3. When the voltage on C3 reaches a certain value, T3 turns on, with the result that the voltage at the output of IC1 ramps negative. The period of the sawtooth is approximately 10 seconds, which may appear rather long. However it is important that the frequency of the sawtooth is much low- er than that of the lowest VCO signal. After being amplified and inverted by IC2 the sawtooth waveform is used as the external tinlebase signal for the scope. The peak-peak value of the volt- age at point A is 16 V. The next step is to derive an exponen- tially related voltage from this saw- tooth, and so this end a diode-resistor matrix, consisting of D3 . . . D6 and R14 Figure 4. Complete circuit diagram of the sweep generator. The exponential converter consists of a diode-resistor matrix. Figure 5. The unijunction transistor for the sawtooth generator can. if desired, be re- placed by two separate transistors. Figure 6. Circuit of a suitable power supply for the sweep generator. ... R21 is used. Basically the matrix forms a voltage divider network in which the size of the input voltage (i.e. A) determines which resistors are in- cluded in the divider chain. As with all exponential converters, the diode-resis- tor matrix provides only an approxima- tion to an exponential signal, however the advantage of this arrangment is that it possesses excellent temperature sta- bility. The output of the matrix is amplified by IC3. The exponential characteristic can be adjusted by means of P4 and P5 — the procedure will be described later in the article. Assuming P4 and P5 are correctly adjusted, a signal which is syn- chronous with the sawtooth and which increases exponentially with time will sweep generator elektor may 1979 — 5-31 be present at point B. Oscillator The actual sweep signal is generated by IC4, a function generator type XR 2206. A detailed description of this IC was contained in Elektor 33 (January 1977). The input of the IC is protected against excessively large voltages by diodes D7 ... D9 and R31. The IC has two outputs which provide a signal of the same frequency. Depending upon the position of S3, the output at pin 2 (point C) will be a triangle or sine- wave, whilst pin 1 1 (point D) provides a symmetrical squarewave. The range switch, S4, provides five frequency ranges (1-10 Hz, 10-100 Hz, 100-1 kHz, 1-10 kHz and 10-100 kHz). The ampli- tude of the triangle/sinewave output can be varied by means of potentiometer P7. With S2 in the ‘sweep’ position, the oscillator frequency is controlled by the output of the exponential converter. In the manual position, the circuit func- tions as a conventional function genera- tor, the frequency of which can be ad- justed by means of P6. The sinewave/triangle output is buffered by IC5. This op-amp must be capable of rapidly handling large input signals, therefore a 709 is used, since it has a higher slew rate than the 741 (IC1 ... IC3). The control voltage which deter- mines the amplitude of the sinewave/ triangle signal is fed not only to pin 1 of IC4, but also via R35 to the non-invert- ing input of IC5. This compensates for the effect of the control voltage on the DC component at point C. The buffered sinewave/triangle is fed to a voltage di- vider. By means of S5 the amplitude of the output signal can be varied in 20 dB steps. The circuit is short-circuit proof in all positions of the switch. The reverse-parallel connected transis- tors T4 and T5 form a voltage con- trolled limiter. When the voltage at point E goes high, T4 and T5 receive base current and conduct on negative and positive half cycles of the waveform respectively, so that the sinewave/trian- gle is limited to the saturation voltage of these transistors. This step ensures that the signal is suppressed during the fly- back of the sawtooth. For this reason the voltage at point E is derived from the squarewave oscillator which triggers the sawtooth generator. The XR 2206 also provides a square- wave output (from pin 11), which is buffered by the circuit round T6 and T7. Although this circuit looks rather unusual, it is basically a discrete equiva- lent of the totem-pole output of TTL ICs. Because of the effect of D12, when T6 is turned on the voltage at the base of T7 is lower than that at the emitter, i.e. T7 is turned off. On the other hand, when T6 is turned off, D12 is reverse biased and the base of T7 is at a higher potential than the emitter, so that T7 is The squarewave output is also provided with a switchable attenuator, however, unlike the sinewave/triangle output, there is no suppression of the signal dur- ing the flyback of the sawtooth, since there is basically little point in using the squarewave signal in the ‘sweep’ mode. Trigger output In addition to the X-output and the two function generator outputs, the circuit is also provided with a trigger output, which can be used if the oscilloscope does not have an external timebase in- put. The signal at the trigger output re- mains high for the duration of the sweep, and should thus be fed to the sync input of the scope. The trigger out- put can also be used for the Z-input of scopes which have such a facility, en- suring that the trace is blanked during flyback of the sawtooth. SI is a pushbutton switch, which, as long as it remains depressed, inhibits the sweep. If the button is pressed during a sweep, the cycle is interrupted and the signal at output 1 is suppressed. S3 switches between sinewave and trian- gle waveform at output 1. At the same time it also switches the squarewave sig- nal in and out. The squarewave is only present when S3a is in the triangle posi- tion. This prevents pulse spikes being superimposed upon the sinewave output because of crosstalk between the two outputs. Construction Care is required in the construction of the sweep generator. Of particular im- portance is the circuit around IC5, since, in order to obtain a high slew- rate, this op-amp is somewhat under- compensated. This means that it may well exhibit a tendency to oscillate and to counteract this effect R38 has been included. Capacitors C14 and CIS should be mounted as close to the IC as possible. For potentiometer P6, used to vary the frequency when the generator is used in the manual mode, it may be advanta- geous to use a multi-turn type with slow motion drive, thus permitting accurate adjustment. Should the unijunction transistor prove difficult to obtain in certain areas, the following alternatives are offered: 2N492, 2N1671, 2N2418, 2N2420, 2N2422, and a further possibility is the TIS 43. In addition it is also possible to replace the UJT by two separate transis- tors as shown in figure 5. The sweep generator requires a power supply which can provide + and — 15V at 300 mA. A suitable circuit is shown in figure 6 and this can be built on the EPS 9968-5 printed circuit board. Calibration The sweep generator has eight preset po- tentiometers, and before beginning the calibration procedure they should all be set to their mid-positions. The same also holds for the control potentiometers, P6 (frequency) and P7 (amplitude). S5 should be set for minimum attenuation, and S2 to ‘manual’. With S3 in the ‘tri- angle’ position, there should be both a triangular waveform at output 1 and a squarewave at output 2. With S2 in its alternative position the squarewave should be absent. By means of P7 it should be possible to vary the amplitude of the triangle wave- form by at least a factor of 10. Should this not be the case, then a smaller value should be chosen for R33. Similarly, with the aid of P6 it should be possible to vary the frequency by a factor of 10. If this is not the case, both R25 and R26 should be reduced. The symmetry of the triangle and sine waveforms can be adjusted by means of potentiometer P8, whilst the distortion factor of the sinewave can be reduced to a minimum by adjusting P9. For both these procedures an oscilloscope is ne- cessary. Once the sweep generator has been given five minutes to warm up, P10 can be adjusted to give a DC voltage level of 0 V (offset voltage) at output 1 (trian- gle/sinewave). When setting the ampli- tude level with P7 this offset voltage should remain at zero volts, however the value of R35 can be altered if it is found that it does vary. Having set up the function generator and output stages the adjustment of PI ... P5 will complete the setting-up proce- dure. The amplitude of the sawtooth at point A should be adjusted to 16 V peak-peak by means of PI, whilst P2 is used to ensure that the sawtooth is sym- metrical about 0 V. Should it prove ne- cessary, the sawtooth can be attenuated by P3 before it is fed to the X-input of the scope. P4 (amplitude) and P5 (DC voltage level) are adjusted such that the expo- nential voltage at point B varies between + 2.75 V and + 0.54 V. It will be ap- parent that PS also influences P4. Once these two potentiometers have been ad- justed the sweep generator is ready for use. The performance of the circuit - par- ticularly in view of the relatively low cost - is excellent. Within the fre- quency range of 5 Hz to 100 kHz the amplitude of the sweep signal is con- stant ± 0.25 dB; below 5 Hz the ampli- tude increases slightly. The frequency characteristic of the generator is also ex- tremely stable, and the zero voltage setting at output 1 exhibits very little temperature drift. Literature: Simple Function Generator, Elektor 33, January 1978. M 5-32 — elektor may 1979 simple sound effects simple sound effects We have, somewhere in the Elektor laboratories, a sound effects department, although the exact location has yet to be discovered. There was a widely held opinion that it was found during the last Christmas office party but this was eventually discounted because a) the noises were too lifelike and b) it was not possible to simulate them electronically! We usually associate their normal products with the dying shrieks of tortured cats, horrifying howls and a whole assortment of plops, bangs, whistles etc. However on the odd occasion they do produce sounds suitable for publication and, to prove that this department really does exist, here is their latest circuit design. The original design for this rather clever sound effects unit was built into a 19inch rack mounting cabinet which unfortunately tended to overheat to an alarming degree (see ‘workshop heater’ in Elektor number 184) and lacked a little on portability. Further research resulted in the following circuit which uses only two CMOS ICs and is very cheap to build. Despite its modest dimensions it will produce a range of sounds from that of an American police siren to one closely resembling the ‘twittering’ of birds. Sounds simple? As is apparent from the block diagram of the circuit (figure 1), the basic principle is extremely straightforward. The output of a twelve-bit binary counter is converted into an analogue voltage which is used to control a VCO. As the binary output of the counter increases, the control voltage ramps positive, until the counter resets and the voltage falls to zero, whereupon the count resumes and the control voltage once again starts to ramp positive, and so on. The waveform of the control voltage is thus a periodic sawtooth. The VCO produces the actual output signal of the circuit, whose pitch is deter- mined by the instantaneous amplitude of the sawtooth control voltage. An output buffer amplifier ensures that the signal is sufficiently large to produce an audible tone when fed to a loudspeaker. The highly individual nature of the resultant sound is due to an unusual feedback configuration. The output signal of the VCO is not only used as the output of the circuit, but as the clock input of the binary counter. Thus the rate at which the counter steps through each count cycle depends upon the pitch of the output signal. In other words, the higher the sound, the faster it varies in pitch. The result is a repeti- tive beuip-beuip sound which starts each phrase at a low frequency and rises exponentially to a maximum pitch. assorted resistors and diodes. IC2 forms the 12-bit binary counter. The binary value of the 8 lowest order bits (i.e. those bits which change state most frequently) is converted into an analogue voltage by means of resistors R1...R8. The VCO consists of a simple CMOS oscillator (built round N1 and N2) the RC time constant of which is varied by using transistor T1 and a diode bridge as a voltage-controlled resistor. As the control voltage fed to the base of T1 increases, more current is passed through the diodes, with the result that their dynamic resistance falls. The initial frequency of the oscillator is set with the aid of preset potentiometer PI, which is connected in parallel with the diode network. The squarewave output of the VCO is fed both to the clock input of IC2 and to an output buffer. The latter is formed by four of the remaining in- verters of IC 1 connected in parallel. Construction A printed circuit board has been pro- vided for the circuit (see figure 3). As can be seen, due to the low component count, the board can be kept very small. The loudspeaker can be any inexpensive 8 S2 type capable of handling 500 mW. The supply voltage of the circuit can lie between 4.5 and 10 V; at the lowest supply voltage the current consumption of the circuit is only 5 mA, which means that a 4.5 V battery could be used, thereby rendering the circuit port- able. Note that the volume of the output signal is determined by the supply voltage level: the higher the supply voltage the louder the sound. The pitch of the output signal can be adjusted by means of PI. Since the pitch directly determines the rate at which the pitch changes, reducing the resistance setting of PI not only in- creases the pitch of the output signal but also causes it to increase more quickly. At the minimum resistance settings of PI the resultant sound some- what resembles that of a chirping bird. The value shown for PI in the diagram (1 MJ2) is chosen to give the maximum adjustment range. However, if desired any value from 10 k to 1 M may be used, with or without fixed series resistors. H Circuit diagram The circuit diagram of the sound effects generator is shown in figure 2, and as can be seen, it consists of only a couple of readily-available CMOS ICs and a few I simple sound effects Figure 1. Block diegram of the simple sound effects generator. The output of a binary counter is converted into an analogue voltage which is used to control a VCO. The output of the VCO forms both the output signal of the circuit proper and the clock signal of the counter. Figure 3. Printed circuit board for the sound effects generator, on which all the com- ponents, with the exception of the loud- speaker, can be mounted. The circuit can be battery-powered if so desired (EPS 79077). Resistors: Capacitors: Cl = 120 n C2= 100 p/16 V Semiconductors : IC1 = 4049 IC2 = 4040 T1 = BC 547B, BC 107B or equ. D1 . . . D4 = DUS Miscellaneous: LS = loudspeaker, 8 fJ/500 mW SI = pushbutton 5-34 - slektor may 1979 BASIC microcomputer BASKS microcomputer A SC/MP juP with BASIC interpreter It seems safe to assume that the 'BASIC microcomputer' is the cheapest home-construction computer ever described that can be programmed using a higher programming language. The SC/MP is a popular and readily-available microprocessor. Two further good reasons for using it in this microcomputer are that it can readily be incorporated into the Elektor SC/MP system, and that a Tiny BASIC interpreter for this pP is available in ROM (Read Only Memory). The BASIC computer card described in this article contains three circuits that can be used as more or less independent units. The processor section is a fully buffered and self-contained 'CPU card' with provisions for DMA (Direct Memory Access) and multiprocessing. The memory section is also fully independent, and contains the BASIC interpreter (NIBL-ROM) and the address decoder. Communication with the 'outside world' (the Elekterminal, for instance) is taken care of by the third section: the interface. To be fully operational, the computer requires at least one 4K RAM card (RAM = Random Access Memory), as described in Elektor, March 1978. The basic BASIC computer therefore consists of not more than two Eurocard-sized printed circuit boards! The main advantage of a higher pro- gramming language is that there is no need to know the exact details of how the ‘inside’ of the computer works. A minor disadvantage is that a more so- phisticated in- and output unit (‘ter- minal’) is required, with an alphanu- meric keyboard. In other words, a key- board that is similar to that of a type- writer. Furthermore, a serial data flow (‘bit by bit’! ) between computer and terminal is normally required. The Elek- terminal with ASCII keyboard (Elektor, November and December 1978) meets these requirements, and this unit or a 1 Figure 1. Functional block diagram of the INS 8060. Figura 2. Block diagram of the BASIC mi- crocomputar/CPU card. BASIC microcomputer elektor may 1979 — 5-35 similar terminal must be used in con- junction with the BASIC computer. Programming in BASIC is easily learned, but it is not so easy to explain all the details in a few pages. For this reason, no attempt will be made in this article to explain how to program in NIBL (National’s Industrial BASIC Language). The BASIC course, which started in the recent March issue of Elektor, must suf- fice. It explains BASIC in general and, as required, deals with NIBL in particu- lar. Obviously, it was written with this BASIC microcomputer in mind! For this article, software is a side issue. The primary concern is the microcom- puter hardware. However, as stated at the outset: if the aim is to program in BASIC, there is no real need to know how the computer works. Most of the following article would therefore appear to be super- fluous: certainly if one has some expe- rience in programming in BASIC, the components can simply be mounted oil the board and, (after a quick glance at the summary of NIBL statements and commands) everything’s ready to roll. However, NIBL not only offers the pos- sibility of programming in (Tiny) BASIC; it also provides for immediate addressing of the hardware. For this rea- son, it can be useful to know a little bit about the actual circuit... Bird's-eye view of the CPU The SC/MP (Simple Cost-effective Micro Processor) is an 8-bit iiP, with all essen- tial functions integrated on a single chip. As is apparent from the block dia- gram (figure 1), the SC/MP (type num- ber INS 8060) contains four 16-bit registers: the program counter and three pointer registers. These ‘pointers’ play an important part in the (auto-) indexed addressing of the memory and input/ output units. The (8-bit) extension register is of par- ticular interest, since it offers a serial in- and output facility with a minimum of fuss. The cassette interface in the Elek- tor SC/MP system makes full use of this possibility. A UART (Universal Asyn- chronous Receiver/Transmitter), as used in the Elekterminal, can also be made redundant by utilising the SIN and SOUT connections. The status register can also be used for serial transfer of data. The three ‘flag’ connections can be used as outputs; ‘sense A’ and ‘sense B’ are both serial inputs. In fact, NIBL uses Flag 0 and Sense B as serial data out- and input re- spectively. The INS 8060 can address 64k bytes of memory. This requires 1 6 address lines, 12 of which are brought out direct via pins of the IC. The four remaining MSB’s (Most Significant Bits) are ap- plied to four lines on the databus during the NADS (Negative Address Data Strobe, on pin 39). If these four bits are left unused, the SC/MP can address only 4096 bytes of memory. This 4K mem- ory is called a ‘page’; the four MSB’s can therefore be used to address 1 6 pages of memory. The SC/MP will not, of its own accord, ‘turn to a new page’. This requires an explicit instruction in the program. When programming in BASIC, nothing could be simpler: for example, the ‘statement’ PAGE = PAGE + 1 causes the nP to proceed to the next page. DMA and multiprocessing The SC/MP has an extremely useful fa- cility, absent in many other uPs: all the outputs used for writing into memory etc. employ so-called Tri-state logic. This means that they can not only be made ‘hard’ logic 1 or 0; a third state is also possible, where the outputs are ‘floating’ with a high output impedance. In this third state, the processor no longer has any effect on the address- and databus: as far as any other units are concerned it is no longer ‘on- line’! Another microprocessor can then take over (multiprocessing), or a ter- minal can be used for immediate access to the memory. The latter option is nor- mally referred to as DMA, for Direct Memory Access. It is not really the in- tention that the (human) operator should proceed to ‘walk around inside the memory’; the main advantage of DMA is that it can save a considerable amount of (computer-) time when trans- ferring large blocks of data from the memory to peripherals — floppy disc, for instance. Instruction set The SC/MP recognises 46 instructions, divided into nine groups; these instruc- tions can be used in up to five different addressing modes. A detailed descrip- tion of the complete instruction set, with all its variation capabilities, is way outside the scope of this article. It would require pages and pages (both magazine and human memory) and, moreover, it would be rather pointless. After all, this computer can be pro- grammed in BASIC! Detailed information is provided by the manufacturer, in the documentation listed at the end of this article. This not only explains the instruction set, but also contains full details on how to pro- gram in machine language and provides detailed technical information. Block diagram The BASIC card consists of three rela- tively independent sections. In fact, it doesn’t really do justice to this design to call it a ‘BASIC card’, since its uses are by no means limited to a mere BASIC computer. Right from the start, the in- tention was to produce a design with a minimum component count and maxi- mum flexibility for different applica- tions. The final result is all that we had hoped for. The BASIC card is virtually a complete microcomputer: only the program mem- ory must be added. The minimum mem- ory requirement is 2048 bytes (suffi- cient for approximately sixty program lines), or half a 4K RAM card (EPS 9885). Obviously, any other ‘memory’ with the same capacity (or more) will do instead. As illustrated in the block diagram (fig- ure 2), the p.c. board contains three dis- tinct sections. The most important of these is the processor section, consisting of the CPU and associated buffer cir- cuits for the address bus, data bus and the main control signals. These buffer circuits make it possible for the CPU to work with extensive memory and peri- pheral systems. In short, this section is the ideal heart of a larger system. A small but useful extension of the pro- cessor circuit is the RS232C/V24 inter- face. This section is connected to the processor’s flag 0 output and sense B input, which are used as serial out- and input both in NIBL and in various other applications. For instance, this interface opens the possibility of connecting the unit direct to a terminal or teletype. # The processor can itself take care of tl?e necessary conversion from parallel to serial data format and vice versa - if the necessary software is available, that is. The saving in cost of hardware is well worth the additional processor-time re- quired for this conversion. The third and last section on the BASIC card is the Read-Only Memory. The complete NIBL-BASIC interpreter is supplied in a single so-called maxi-ROM. With its 32 Kbit (4096 bytes) memory capacity, this IC represented the abso- lute limit in Large Scale Integration (LSI) until quite recently, when a ROM with a 64 Kbit storage capacity was an- nounced ... It is to be expected that we will see ever larger ROMs appearing for some time to come. The inputs to the ROM represent a neg- ligable load on the address bus, so there is no need to add buffer stages at this point. The ROM outputs, however, have a very low drive capability; for this rea- son, an output buffer is required. The advantage of the system outlined above is that the processor and ROM sections are fully independent units. Al- though both are mounted on the same p.c. board, their only means of commu- nication is via the general system bus - the same bus that is used for communi- cation with any other part of the sys- tem. This means that it is possible, for instance, to fully utilise the processor’s capabilities in a particular application where the ROM is not required. The circuits . The circuits of the processor section and the associated RS232C/V24 interface I are given in figure 3. BASIC microcomputer elektor may 1979 - 5-37 Figure 3. The processor section with input/ output interface. This section can also be used as fully buffered CPU card. Figure 4. Flow diagram of the initial check procedure that precedes each read or write Figure 5. Pulse diagram of the main control signals within the BASIC microcomputer. The interface does two jobs. In the first place, the TTL logic level at the flag 0 output of the processor must be con- verted to RS232C/V24 level. This means that logic 1 must be at least +5V and not more than +15V; similarly, logic 0 must be some level between -5V and -15V. As in the Elekterminal, the logic levels chosen in this circuit are +5V for logic 1 and -12V for logic 0 - for the simple reason that these levels correspond to common supply voltages. The fact that they are asymmetrical with respect to OV has no effect on the realibility of data transfer. The flag 0 output of the processor drives transistor T1 ; in turn, this transis- tor switches a current source (consisting of T3 and a few resistors and diodes). The advantage of using a current source at the output is that it is short-circuit proof. Furthermore, it then becomes re- latively easy to obtain a low output im- pedance, as required by the RS232C/ V24 standard. Should a standard TTL level output be required for some appli- cation, it is sufficient to add one extra diode (D4). Logic 0 will then corre- spond to -0.6V (and logic 1 remains +5V); the interface circuit is then a short-circuit proof TTL output buffer. The second thing the interface must do is limit the logic levels at the sense B input of the processor. This is easily ac- complished by T2 and D3; R14 limits the input current to a comfortable level. The basic principles of the processor section have already been explained. However, some further explanation of the circuit is called for - particularly where the Direct Memory Access and multiprocessing facilities are concerned. The CPU, or Central Processor Unit, (IC1 ) receives clock pulses from an inter- nal oscillator, with an external crystal to determine the frequency. From this clock signal, the NRDS (Negative Read Data Strobe) and NWDS (Negative Write Data Strobe) are derived. The address and data outputs of the CPU have a limited drive capability. For this reason, the address bus is buffered by IC2 and IC3; similarly, IC4 and IC5 are included as databus buffer. These four ICs have an interesting feature: the input circuits incorporate PNP transis- tors in such a way that the input current is limited to 100 p A. A shift register (IC6) is used as a buffer memory for the four highest address bits (MSBs). Using the 74LS95 at this point has the advantage that the NADS (Negative Address Strobe) can be used, without need for an inverter, to read in the four MSBs to the register. The NADS is also used to control the databus buffers, in conjunction with the NRDS and NENOUT signals (Negative Read Data Strobe and Negative ENable OUTput, respectively). This combina- tion may seem rather strange to those of our readers who have previously studied the Elektor SC/MP system. One would expect that the NWDS (Negative Write Data Strobe) would also be involved in the control of the databus buffers. After all, the NWDS is supposed to control 5-38 - elektor may 1979 BASIC microcomputer the storing of data in memory. Rest as- sured: that is still the case, even with this system. The only difference is that the NWDS no longer determines the moment when the data is applied to the databus. The timing sequence is such that the data is already present at the memory inputs before the NWDS signal initiates the writing of that data into the memory. The advantage of this system is that it makes for a more reliable ‘write’ cycle. Reading data out of the memory is done in the usual way: the databus buffers are controlled by the NRDS. When addressing memories and the like, a sig- nal is used that is derived (as in the Elektor SC/MP system) by ANDing the NRDS and NWDS signals, in Nl. These two signals are also brought out sepa- rately to the system bus via N2 (NWDS) and N4 (NRDS). It should be noted at this point that both the 74(LS)08 and the 74(LS)09 can be used as output buffers; the 09 is only required in DMA or multiprocessor systems. The reason for this is that the 74(LS)09 has so-called open-collector outputs, so that several of these ICs can be connected in parallel (with one com- mon set of pull-up resistors) without ‘biting’ each other. If only a simple sys- tem is contemplated, with one CPU and without DMA, the 74(LS)08 can be used instead; the pull-up resistors Rl, R2, R3 and R5 can then be omitted. There is a further reason for controlling the databus buffers by means of a com- bination of the NADS, NRDS and NEN- OUT signals - quite apart from the in crease in speed and reliability when writing data into the memory. In sys- tems where the SC/MP is used without output buffers, DMA and multipro- cessing present few problems, since its tri-state outputs can easily be set in the ‘floating’ mode. However, in the buf- fered system described here, the output buffers are not controlled by the NWDS signal; they could easily remain in the ■write’ mode, forcing ‘hard’ logic levels onto the databus. This possibility is pre- cluded by using the NENOUT signal to terminate the ‘write’ mode. In order to understand how this works, the ‘read’ and ‘write’ cycles in the SC/MP system must be explained in slightly greater de- tail. Reading and Writing As is often the case, the best place to start this explanation is at the be- ginning: logic 0 level at the NRST input (Negative ReSeT). This situation is achieved by operating SI. The set/reset flip-flop (N7, N8) applies logic 0 to the NRST input of the SC/MP for as long as this key is held down, causing the pro- cessor to assume its initial (reset) state. All outputs, with the exception of the NENOUT (Negative Enable OUTput), are then in the floating (tri-state) mode. The pull-up resistors R4, R6 and RIO hold the NWDS, NRDS and NADS out- puts at a defined logic level (logic 1 ), so that nothing untoward can occur... When SI is released, the SC/MP will check for a logic 0 level at the NBREQ and NENIN inputs (Negative Bus RE- Quest and Negative ENable INput, re- spectively). Figure 4 illustrates this pro- cedure. In a basic single-processor sys- tem without DMA facility, R7 will al- ways pull the NBREQ input high. As soon as the processor detects this logic 1 level, it will proceed to use the same connection as NBREQ output. Since the logic 1 level signifies that no other part of the system is using the bus at present (obviously, in a simple system without DMA this is always the case, since there is only the one CPU), the processor pro- ceeds to stake its claim to the bus by making the NBREQ output logic 0. Having done this, it tests the logic level at the NENIN input. Since this input is connected to the NBREQ output (by means of the link shown as a dotted line in figure 3) it will also be at logic 0 level. With both necessary conditions now fulfilled, the SC/MP will proceed to fetch its first instruction. This first ‘read’ cycle is illustrated in fig- ure 5. Shortly after the NBREQ output goes to logic 0, the NADS signal ap- pears. The shift register (IC6 in figure 3) takes this as its cue to store the four MSBs of the address; simultaneously flip-flop N5/N6 is set, switching the databus buffers into the write mode. However, when the NRDS signal ap- pears it will reset this flip-flop and switch the databus buffers into the ‘read’ mode. The read cycle is ter- minated by a brief pulse on the NEN- OUT connection. In this case, the NEN- OUT pulse has no effect on the buffers — they had already been switched back to the floating state at the end of the NRDS pulse, as shown in figure 5. The sequence of operations during the write cycle is similar, with one major difference: the output of N6 holds the databus buffers in the write mode for a much longer period. In fact, the NWDS signal falls well inside this period. The result is that the data to be stored are present at the memory input well before the NWDS signal appears, and remain there for a short time after this pulse is terminated. Finally, the NENOUT pulse causes the buffers to revert to the float- ing state. The advantage of the system outlined above will become apparent from a closer look at the multiprocessor facili- ties that the SC/MP has to offer. Figure 6a gives a rough outline of a microcom- puter system in which several SC/MPs are used. The first of these is connected in the same way as in the single-proces- sor system described so far. For all the following SC/MPs, however, there is a minor modification to the circuit: the NENIN input of each is connected to the NENOUT of its predecessor in the BASIC microcomputer elektor may 1979 — 5-39 ■7 41612 chain. After the initial reset, the situation for the first processor is exactly as outlined above. All other processors, however, must wait for their turn: as long as one CPU is using the bus, all others must keep off. The principle is clear from fig- ure 4: each time a CPU wants to ‘get on the bus’, it will first check the logic level on its NBREQ input. A logic

, =, < =, >=,<>. - logic operators: AND, OR, NOT. - decimal constants must remain with- in the range from —32767 to +32767. - hexadecimal constants are recognised as such when preceded by the sym- bol #. Not more than four digits ( 1 6 bits) are permitted. - program lines may contain more than one statement, provided the state- ments are separated by a colon (:). Functions - RND (a, b) generates a random num- ber within the range from a to b. - MOD (a, b) gives the remainder after the division a/b. ST AT calls up the contents of the status register in the SC/MP. - PAGE calls up the number of the page in memory that is currently in use. - TOP calls up the upper boundary of the NIBL program, as a decimal ad- dress. INPUT/OUTPUT statements - INPUT X - INPUT X, Y,Z - PRINT ’’THIS IS NIBL” - PRINT ”F = ”,M * A - PRINT ’’SKIP”, X, ’’PAGES”; Note that the semicolon (;) suppresses the automatic CR/LF (Carriage Return/ Line Feed) after a print statement. 5-42 - elektor may 1979 10 Assignment statements - LET X = 7 - E = I * R - STAT = # 70 - PAGE = PAGE + 1 - LET <$ A = 255 - (a (T + 36) = # FF - B = (& ! (TOP + 5) Control statements - GOTO 15 or GOTO 15 - GOTO X + 5 - GO SUB 100 or GOSUB 100 - RETURN - IF X + Y > # 1 A GOTO 15 - IF A = B LET A = B-C - FOR I = 10 TO 9 STEP -2 - NEXT 1 - FOR K = 1 TO 5 - DO: X = X + 1 : UNTIL (X = 10) OR (@X= 13) Indirect operator - the (<“ symbol can be used for imme- diate addressing of a location in memory; for instance: V = # 2000: LET