up -to-date electronics for lab and leisure BLeMTOr IS Time on TV $ Score on TV Loud mouth October 1976 40p 1002 — elektor October 1976 publisher's notices elektor decoder What is a TUN? What is 10 n? What is the EPS service? What is the TQ service? What is a missing link? Semiconductor types Very often, a large number of equivalent semiconductors exist with different type numbers. For this reason, 'abbreviated' type numbers are used in Elektor wherever possible: - '741' stands for pA741, LM741, MC741, MIC741, RM741.SN72741.etc. - 'TUP' or 'TUN' (Transistor. Universal, PNP or NPN respectively) stands for any low frequency silicon transistor that meets the specifications listed in Table 1 . Some examples are listed below. - 'DUS' or 'DUG' (Diode, Universal, Silicon or Germanium respectively) stands for any diode that meets the specifications listed in Table 2. - 'BC107B', '8C237B', ’BC547B' all refer to the same 'family' of almost identical better-quality silicon transistors. In general, any other member of the same family can be used instead. (See below.) For further information, see 'TUP, TUN, DUG, DUS', Elektor 17, p. 948. Table 1 . Minimum specifications for TUP (PNP) and TUN (NPN). 20V 100 mA 100 100 mW 100 MHz Some "TUN's are: BC107, BC108 and BC109 families; 2N3856A, 2N3859, 2N3860, 2N3904, 2N3947, 2N4124. Some 'TUP'S are: BC177 and BC178 families; BC179 family with the possible exception of BC169 and BC179; 2N2412, 2N3251, 2N3906, 2N4126, 2N4291. Table 2. Minimum specif ications for DUS (silicon) and DUG (germanium). DUS DUG v R,max JR, max Ptot.max CD.max 25V 100mA IpA 250mW 5pF 20V 35mA 100 m A 250mW IQpF SomeDUS's are: BA127, BA217, BA218, BA221, BA222, BA317, BA318, BAX13, BAY61, 1N914, 1N4148. Some 'DUG's are: OA85, 0A91.0A95, AA116. BC107 (-8, -9) families: BC107 (-8, -9). BC147 (-8. -9), BC207 (-8, -9), BC237 (-8, -9), BC317 (-8, -9), BC347 (-8, -9), BC547 (-8,-9), BC171 (-2, -3), BC182 (-3, -4), BC382 (-3, -4), BC437 (-8,-9), BC414 BC177 (-8, -9) families: BC177 (-8. -9), BC157 (-8, -9), BC204 (-5. -6), BC307 (-8, -9). BC320 (-1, -2). BC350 (-1, -2). BC557 (-8. -9), BC251 (-2, -3). BC212 (-3, -4), BC512 (-3, -4). BC261 (-2, -3). BC416. Resistor and capacitor values | When giving component values, decimal points and large numbers of zeros are avoided wherever possible. The decimal point is usually replaced by one of the following international abbreviations: p (pico-l * 10‘ ia n (nano-) = 10'* M (micro-)= 10"‘ m (milli-) = 10° k (kilo-) - 10 s M (mega-) = 10‘ G (giga-) =■ 10* A few examples: Resistance value 2k7: this is 2.7 kll, or 2700 SI. Resistance value 470: this is 470 n. Capacitance value 4p7: this is 4.7 pF. or 0.000000000004 7 F ... Capacitance value 10 n: this is the international way of writing 1 0,000 pF or .01 pF, since 1 n is 10"’ farads or 1000 pF. Mains voltages No mains (power line) voltages are listed in Elektor circuits. It is assumed that our readers know what voltage is standard in their part of the world! Readers in countries that use 60 Hz should note that Elektor circuits are designed for 50 Hz operation. This will not normally be a problem; however, in cases where the mains frequency is used for synchronisation some modification may be required. Technical services to readers - EPS service. Many Elektor articles include a lay-out for a printed circuit board. Some - but not all - of these boards are available ready-etched and predrilled. The 'EPS print service list' in the current issue always gives a complete list of available - Technical queries. Members of the technical staff are available to answer technical queries (relating to articles published in Elektor) by telephone on Mondays from 14.00 to 16.30. Letters with technical queries should be addressed to: Dept. TQ. Please enclose a stamped, self addressed envelope; readers outside U.K. please enclose an IRC instead of - Missing link. Any to, additions to, improvements on or corrections in Elektor circuits are generally listed under the heading 'Missing Link' at the earliest opportunity. ei.eHTnr m Volume 2 Number 10 Editor : Deputy editor Technical editors : Art editor Drawing office Subscriptions W. van der Horst P. Holmes J. Barendrecht G.H.K. Dam E. Krempelsauer G.H. Nachbar Fr. Scheel K. S.M. Walraven C. Sinke L. Martin Mrs. A. van Meyel UK editorial offices, administration and advertising: 6 Stour Street, Canterbury CT 1 2XZ. Tel. Canterbury (0227) - 54430. Telex: 965504. Bank: Midland Bank Ltd Canterbury A/C no. 11014587, Sorting code 40-16-11. giro: no. 3154254. Assistant Manager and Advertising : R.G. Knapp Editorial : T. Emmens Elektor is published monthly on the third Friday of each month, price 40 pence. Please note that number 15/16 (July/August) is a double issue. 'Summer Circuits', price 80 pence. Single copies (including back issues) are available by post from our Canterbury office to UK addresses and | to all countries by surface mail at £ 0.55. Single copies by air mail to all countries are £ 0.90. Subscriptions for 1976 (January to December inclusive): to UK addresses and to all countries by surface mail: £ 6.25, to all countries by air mail £ 11,-. Subscriptions for 1976 (November and December): to UK addresses and to all countries by surface mail: £ 1.05. All prices include p & p. Subscribers are requested to notify a change of address four weeks in advance and to return envelope bearing previous address. Letters should be addressed to the department concerned: TQ = Technical Queries; ADV = Advertisements; SUB = Subscriptions; ADM = Administration; ED - Editorial (articles submitted for publication etc.); EPS = Elektor printed circuit board service. For technical queries, please enclose a stamped, addressed envelope. The circuits published are for domestic use only. The submission of designs or articles to Elektor implies permission to the publishers to alter and translate the text and design, and to use the contents in other Elektor publications and activities. The publishers cannot guarantee to return any material submitted to them. All drawings, photographs, printed circuit boards and articles published in Elektor are copyright and may not be reproduced or imitated in whole or part without prior written permission of the publishers. Patent protection may exist in respect of circuits, devices, components etc. described in this magazine. The publishers do not accept responsibility for failing to identify such patent or other protection. Distribution: Spotlight Magazine Distributors Ltd., Spotlight House 1, Bentwell road, Holloway, London N7 7AX. Copyright © 1976 Elektor publishers Ltd - Canterbury. Printed in the Netherlands. contents selektor 1006 score on screen for TV games 1008 Although the MM5841 1C. described elsewhere in this issue, is primarily intended to display time and TV channel number on a TV screen, it may of course be used to display any other numerical information that is fed into it. The 1C is thus ideal for displaying the score in TV games (e.g. Elektor TV Tennis), as described in this article. FM on 11 meters 1013 In earlier issues of Elektor (February and April 1975) it was explained why frequency modulation is one of the most efficient methods of modulating a carrier wave. To prove the point, not only by theoretical but also by experimental demonstration, this article describes the design and construction of a practical model intending to bear out the correctness of the abovementioned statement. autoranger for DFM — R. Decker 1018 This circuit automatically selects the optimum gate period for a frequency measurement, positions the decimal point in the display and indicates the units of the measurement (Hz, kHz, MHz). time on TV 1022 The current trend in the TV industry seems to be the proliferation of 'gadgets' for use with the TV set, and the use of the TV screen to display information other than pictures. Typical examples of this trend are the sophis- ticated ultrasonic remote control units currently available. Teletext, and of course TV games. This article takes a look at two IC’s that can be used to display the time on a TV screen. alignment squeaker 1029 or an 'audible signal-strength indicator' SQ decoder 1030 Last month we published the circuit of the SQL-200 SQ decoder, with a printed circuit board design as sup- plied by CBS. Since our circuit board design staff felt they could do a better job (!), they were given the go- ahead. The new design, as published here, will now be made available through the EPS service. digits on TV — W. Frenken 1034 This circuit can be used to display a row of up to eight digits on a TV screen. It gives a video output consisting of horizontal and vertical synchronisation pulses and the black/white pattern corresponding to the digits in seven segment format. It will accept an eight-digit parallel input and, as an example, the circuit of an eight-decade frequency counter Leading-zero blanking is included in the design. dual voltage regulators 1040 In the article 'Integrated Voltage Regulators' (Elektor 1 1 and 1 2) positive and negative 1C voltage regulators of both fixed and variable voltages types were discussed. This article is intended as a follow-up and looks at dual regulator ICs (i.e. those that provide both a positive and a negative output). Practical designs are presented for laboratory power supplies providing up to i 30 V at 2 A. the LOUD mouth 1048 Loud hailers are used wherever people need to make themselves heard over a large distance. The design described here is meant for use in cars and thus derives its power from the car battery. This means that the maximum voltage available is only 12 volts, so some unconventional circuits are required to produce sufficient audio output power. improved current source 1052 market SSOffQ @(n) SSffQQOn tew W gsosss Although the MM5841 1C, described elsewhere in this issue, is primarily intended to display time and TV channel number on a TV screen, it may of course be used to display any other numerical information that is fed into it. The 1C is thus ideal for displaying the score in TV games (e.g. Elektor TV Tennis), as described in this article. Before reading this article it is essential to read the article Time on TV', elsewhere is this issue, in order to understand the operation of the MM5841 . In the Time on TV’ article it wa, explained how the MM 5 841 could ac ( cept up to eight digits in inverted BCD code (hours, minutes, seconds and Tl channel number) and write them on thi TV screen. To display the score of a T\ game, the MM5841 is fed with infot mation from score counters instead o from a digital clock. The other mail difference is that no internal connec tions are required to the TV, as was thl case with the time display. Since th picture is being generated by the T' game the output of the scoring unit cat simply be fed into the video mixer alonj with the rest of the picture information and thence to the modulator. Figure 1 shows a block diagram of thj scoring unit. The circuit contains two twin decadl counters (block D) that register thj score for each player. These counter receive clock pulses from the ‘T\ Tennis’ extensions board described ii Elektor No. 13. Which counter receivesj clock pulse depends on which player hai scored the point, and this is also deteil mined by control signals from thj extension board. Altogether there are five inputs to thl scoring unit from the extension boara Two of these are simply line and fiell comroi me ummg sequence oi i1, MM5841 . The other three are with the score counting. Referring to issue 13, readers will no remember that a score point is mined by the Q output of FF3 ure 15) going high. This triggers score sound effect circuit in figure 1 1010 — elaktor October 1976 is scored then if the ball is travelling to the left the Q output of FF2 is high and the point is obviously scored by the right-hand player. On the other hand if the ball is travelling to the right the Q output of FF2 is high and the point is scored by the left-hand player. The Q and Q outputs of FF2 are used to gate the clock pulse into the right and left- hand score counters respectively (via counter selector block E). The Q and Q outputs of FF2 are available on the edge of the extension p.c. board at points O and J. Parts list Resistors: R1 ,R2 = 10 k R3,R4 = 18 k R5,R12,R13,R14 = 33 k R6.R7.R1 5 ... R21 ,R24 = 470 fl R8 ... R1 1 ,R22,R23 = 1 k Capacitors: Cl ,C3= 100 n C2 = 1 u C4 = 820 p C5 = 5p6 C6 = 22 n C7 ... C10 = 1 n Decoupling: C x = 100 n C y = 100#i. 10 V Semiconductors: T1 ... T4 = TUN D1 ... D27 = DUS ICs: IC1 = MM5841 IC2 = CD4011 IC3 = 7406 IC4 ... IC7 = 7490 IC8 ... IC11,IC14,IC15,IC17- 7408 IC12 ■= 7404 IC13.IC18 = 7427 IC16 = 7400 Miscellaneous: PI ,P3 = preset potentiometer 100 k P2 = preset potentiometer 47 k 51 = push-button switch n.o. contact 52 = six-way 2-pole switch Figures 3 and 4. Printed circuit board and component layout for the complete circuit (EPS 9405). | The outputs of the score counters must I be multiplexed before they can be fed j into the MM5841. This operation is I controlled by the digit address’ outputs of the MM5841, via a CMOS/TTL level shifter block C. There are two outputs from the scoring unit. One of these is the video signal that comprises the score, and the other is a ‘score limit’ output that prevents the ball from being served after one of the players has reached a preselected maximum score. This can be set to 10, 20, 30, 40, 50 or 60. score on screen for TV games Pulse shaper, counter selector and counters The complete circuit of the scoring unit is given in figure 2. The SCO input arrives at the input of N39 and triggers a monostable comprising N39 and N38. The output of this is buffered and inverted by N37. The clock pulse is routed either to the input of the right- hand score counter (IC4, ICS) via N36,| or to the input of the left-hand score! counter (IC6, IC7) via N35, depending on the state of FF2. The score counters; three-input NOR gates N31 to N34, which perform the digit selection, e.g. N31 has inputs X, Y and Z. When the digit address is 000 (all three inputs low) then the output of N31 will be high and the outputs of 1C4 will be selected. N32 has inputs X, Y and Z, so when X is high and Y and Z are low the inputs of N32 will be low and the out- put high, so the outputs of 1C5 will be selected, and so on. Video output and unused digit blanking The MM 5841 has facilities for dis- playing up to 8 digits when used in the normal time and TV channel mode, but of course only four digits are used in this application. For this reason it is used in the ‘four-digit, time only’ mode. However it will then still give a colon between the two pairs of digits, which must also be suppressed. This is ac- complished by blanking the video out- put of the MM5841 except when one of the used digits is selected. The video output appears at pin 15 of the IC and is CMOS to TTL level-shifted by T4 then fed to AND gate N13. The other input of N13 is connected to the output of a diode OR gate comprising D24 to D27, whose inputs are fed by the outputs of N31 to N34. Only when one of the outputs of N31 to N34 is high will the input (pin 1) of N13 be high and the video signal will be allowed through. At all other times the video signal will be inhibited. The video signal is fed via diode D4 to point A of the video mixer, where it is combined with the rest of the picture information. 4 MHz Clock This differs slightly from the circuit used in the ‘Time on TV’ article. CMOS NAND gates are again used, but as CMOS gates are not used anywhere else in the circuit there are two spare gates available in a 4011 package, and these are incorporated into the clock oscil- lator (block A, figure 2). This intro- duces two propagation delays into the timing sequence, so the value of the timing capacitor is reduced. The fre- quency can be varied by P3 to alter the width of the digits in the display. Vertical and horizontal position As in the ‘Time on TV’ circuit, the vertical and horizontal position of the display may be altered by PI and P2. Sync inputs As explained in the ‘Time on TV’ article, the logic levels for the sync inputs of the MM5841 are unusual, the logic 0 or low level being typically Vdd - 5 V (in this case 9 V) instead of the more usual Vss (0 V). These inputs must be interfaced with the TTL outputs of the sync circuits of the TV Tennis. Fortu- nately this is easily accomplished by holding the sync inputs normally at +9V by potential dividers R1/R3 and R2/R4. The sync pulses are then A.C. coupled through Cl and C2. may be reset to zero by S 1 . Digit selection On the four outputs of each counter stage are four AND gates wired as trans- fer gates. These allow one digit at a time to be selected and fed into four four- ' input OR gates comprising D8 to D23 and R 1 8 to R2 1 . The outputs of the OR gates are inverted to convert the data to the inverted BCD code required by the MM5841. The inverters N7 to N10 have high-voltage open-collector outputs, and | the collector load resistors are taken to the +14 V rail so that the inverters also provide a TTL to CMOS logic level shift. Selection of the counter output to be fed into the MM5841 is controlled by the digit address outputs of this IC. The digit address (X, Y and Z) outputs are connected to T3, T2 and T1 respect- ively, which perform a CMOS to TTL level shift. The outputs from the emit- ters of these transistors are buffered by inverters N1 to N6, and the X, Y and Z outputs and their complements are available. These are used to control 1012 — elektor October 1976 score on screen for TV games At this point it should be noted that the values of R1 . . . R4 are critical. If there are problems with the sync, try increas- ing the values of R3 and R4 to about 20 k. Score limiter When the preselected maximum score is reached the score limiter inhibits mono- stables IC1 and IC2 that produce the ball signal on the main TV Tennis board. Referring to issue 11 p319 figure 1 , the output of the score limiter is connected to points 8 and 9. The out- put of the score limiter is normally high, so the B’ inputs of IC1 and 1C2 are high and the monostables function normally. When the maximum score is reached the output of the score limiter will go low and the monostables can no longer be triggered. The score limiter (block G) is connected to the outputs of the highest decade of the left and right score counters, and the maximum score is selected by S2. For example, with S2 in the first pos- ition the A output of IC7 is connected to the input of N43. When the left- hand player’s score reaches 10 first this output will go high and the output of N43 will go low, inhibiting the ball signal. If the right hand player is the first to score 10 then the A output of ICS will go high and the output of N47 will go low, inhibiting the ball signal. For a score of 20 the B outputs of the counters are used. For a score of 30 the A and B outputs are ANDed together and so on, up to a maximum score of 60. Construction A p.c. board and component layout are given in figures 3 and 4. Construction is quite straightforward and no prob- lems should be experienced provided the usual precautions are taken for handling CMOS. Apart from power supply connections and switches the only external connections are to the rest of the TV Tennis circuitry, and these connections are detailed in figure 1 . All the connection points will be found along the edge of the extension printed circuit board, with the exception of points 8 and 9, which are on the main p.c. board. The power supplies for the scoring unit may be obtained from the supplies in the existing game. The +5V may be obtained from the +5 V rail on the | extension board. The +14 V rail may conveniently be obtained from the +18 V supply to the sound effects I amplifier by using a simple series regu- lator. Make sure this voltage does not exceed 15 V, or the chips may be damaged. The current consumption is only about 15 mA. Adjustments The adjustments to the scoring unit are made by P3, which adjusts the character I width, and PI and P2, which adjust the position of the display on the TV screen. H FM on 11 meters elektor October 1976 — 1013 (MO ©(H) 00 ©©tecs In earlier issues of Elektor (February and April 1975) it was explained why frequency modulation is one of the most efficient methods of modulating a carrier wave. To prove the point, not only by theoretical but also by experimental demonstration, this article describes the design and construction of a practical model intending to bear out the correctness of the abovementioned statement. The transmitter circuit described is intended to be used in the 27 MHz citizen band but will also produce good results in the hands of a 28 ... 30 MHz narrow band FM operator. Its frequency stability is sufficient for the purpose and the output power (250 mW) is enough to establish reliable communi- cations over short distances. The re- ceiver circuit shown in this article is of a quite unsophisticated design but nevertheless will give a good account of itself. The entire system would lend itself admirably to such applications as wire- less microphones, intercoms, baby alarms, and so on, if it were not for just one little snag: at the present time, regrettably, radio transmissions in this band are legally restricted. The experimenter is advised to operate in a closed circuit mode, via a suitable length of coaxial cable, to avoid getting into trouble with the law. The 27 MHz citizens band The original use of this band was to meet the need for inexpensive wireless telephone links for industrial purposes in the USA. As the interest in this band spread, the initial purpose became more obscure and the use of the band became more general. As more and more people came onto the citizens band, congestion and channel crowding became more the rule than the exception, forcing the industrial users to move out of the band. Over the past 10 years the CB situation in the United States has become a free- for-all where the majority of users com- pletely ignore the rules set down by the FCC. However, during the last year there seems to be a upswing of law abiding operators coming onto the band. Fundamental differences exist between the fields of interest of the average citizen band operator and the fully licensed radio amateur. The amateur Figure la. Block diagram of the transmitter. Figure 1b. Simplified diagram of the output stage showing phase relationships between input and output signals. 1014 — elektor October 1976 FM on 11 licensee has the technical know-how and ability needed to obtain a license, whereas some CBers may not know the difference between the mains connector and the microphone . . . Furthermore, the licensed radio amateur may be roughly divided into two groups: the ‘software’ category, or those who take the design of their equipment for granted and are intent mainly on the communications, and the ‘hardware’ category mainly interested in the elec- tronic aspect of their gear. The availability of so much off-the-shelf equipment may discourage the techni- cally minded operator from keeping abreast of new developments in the field of electronics. The present article is intended to stimulate those who would like to be experimenting again, although we are well aware of the fact that the equipment described will probably not find immediate practical applications. The transmitter The block diagram is shown in figure 1 a. The input stage is a speech compressor/ amplifier. This reduces the effect of variations in the speaker-to-microphone distance and, at the same time, prevents overmodulation. A suitable compressor design was described in Elektor, April 1975, p. 440. After pre-emphasis, the signal modulates the varicap oscillator. The second har- monic of the oscillator frequency is fed to a frequency-doubler output stage. This functions as follows (figure lb). Transistor T1 and T2 are driven in anti- phase, each one being conductive only when the driving signal exceeds the 2 v be A 1- a . ^1 V/ ' — - 20 kfi/V) between the positive lead of C29 and supply common. Connect the appro- priate resistive network shown in fig- ure 2 to Lj and Rj. Drive a constant music signal, or a 1 kHz sinewave into the network. While the audio is applied, note that if R73 is rotated from one end to the other end, the voltage of C29 varies from a high level (8 volts or more) down to almost 0 volts. This indicates the correct performance. Now, set the potentiometer so that C29’s voltage just reaches the lowest value. You will find 3 | 40n'm 1 1 ) 2 " 1 y - »™l 3 /.l i ft ft 1 5mml 3 /l6"l 9494.4 1 K- 1 this setting to be very sensitive . . . this is because you are setting the threshold at which the FET switches (when T12 drops to near 0 volts) and the gain of T12 is very high. For further checkout and operating suggestions, see the previous article in Elektor 17. Figure 1. Complete circuit of the SQ logic Figure 2a. Network for variable-blend adjust- ment when using a 1 kHz sine-wave. The out- puts from this network are fed to the Ly and Rj inputs of the decoder. Figure 2b. Network for variable-blend adjust- ment when using a music source. Figure 3. This brass shield should be mounted on the p.c. board between the mains trans- former and the output amplifiers. A small piece of printed circuit board can also be Figure 4. Component layout and p.c. board for the decoder. 1034 — elektor October 1976 digits on TV (°)0©8te ®oi i W W. Frenken This circuit can be used to display a row of up to eight digits on a TV screen. It gives a video output consisting of horizontal and vertical synchronisation pulses and the black/white pattern corresponding to the digits in seven segment format. It will accept an eight-digit parallel input and, as an example, the circuit of an eight-decade frequency counter is also given. Leading-zero blanking is included in the design. There are numerous applications for a circuit that will display digits on a TV screen. The maximum number of digits that will fit on the screen depends, of course, on the size chosen. For most applications the size chosen here should be suitable: eight digits over the full width of the screen. In principle, the system can be used to give up to five rows, or a total of 40 digits. However, in this circuit the display is limited to one row. The digits are ‘written’ on the screen as a pattern of white dashes, stacked verti- cally on top of each other. The European TV system has 625 lines for each complete picture, and each picture is built up in 40 ms (two ‘fields’ of 20 ms each). This means that each line takes 64 /ts. The line sync pulse takes 12 /is, leaving 52 /ts for the visible portion of each line. It so happens, as we will see later on, that it Simplifies matters to use mul- tiples of 1 /is for all the time-slots. Since we want eight digits in a row, with gaps between them, an obvious ‘binary’ choice is 2 /is per digit with 2 /is gaps. This will give digits that are nearly one inch wide (2 cm) on a large screen. The seven-segment digits are built up as shown in figure 1. Letters A to G indicate the seven segments, and each digit consists of two or more of these segments. Since the digit width is 2 /is, the shortest time-slots (tl and t3) are only 16 /is — but this will not present any problems. The next point is to choose the correct height. The height of one vertical unit (LI, for instance) should be the same as one horizontal unit. The horizontal unit is Vi /is, which is times the length of one line - the duration of one (visible) line is 52 /is. Since the width-to-height relationship of a TV picture is 4:3, the ■vertical unit’ must be 4 (312.5 -20)_, visible field is 20 lines). This is not easy to obtain, so 4 lines are used instead - a nice round binary number ... The digit height is then 24 lines per field (48 lines per picture), or just over one inch (3 cm). Timebase generator The first requirement for a stable pic- ture is that it is built up at a speed that is ‘TV compatible’. Furthermore, the digit generator and the television set must run in synchronism. Both require- ments can be met by using a sync gener- ator that runs at normal TV speed, and using this to generate the digit pattern. The basic timebase is shown in figure 2. The clock generator consists of N 1 and N2 with the 1 MHz crystal. This drives a divide-by-eight counter (FF1 to FF3) which, in turn, drives a second divide- by-eight counter (FF4 to FF6). The total division ratio is therefore 64, so that the output period time is 64 /is - the line frequency. The simplicity of this division is one of the main reasons for choosing 1 /is as the basic time unit! At this stage, it is interesting to mention the so-called octal way of counting. Since binary systems work in powers of 2, basic counts are 2, 4, 8, 16, 32, etc, corresponding to the basic counts in ‘normal’ decimal counting of 9, 99, 999, etc. ‘Octal’ counting groups three basic binary counts together, and uses decimal numbers. The basic counts are then 7, 77, 777, etc. To give a few examples: binary 1 is octal 1 ; binary 1 1 is octal 3; binary 101.110 is octal 56. To distinguish octal numbers from decimal numbers, an extra 8 is added, thus: 56g (octal) = 46 (decimal). The two divide-by-eight (= octal) counters therefore count from 00 8 to 77g. The total picture consists of 625 lines and two fields. This means that the field synchronisation is required every 312.5 lines, or, to put it differently, every 625 half-lines. The output of FF5 corre- sponds to half-lines. This output is connected to four divide-by-five coun- ters in cascade (IC4 . . . IC7). The out- put of FF7 can now be used for field sync. Sync generator The actual sync signals required are rather more complicated. The outputs of the counters FF1 to FF6 and IC4 to IC7 are connected to the video gener- ator shown in figure 3_. The line sync pulse LSY (output from N27) is derived from Q3 to Q6, so it lasts from 1 1 1 100 to 111111, or 74g . . . 77g, which is 4 /is (see table 1 and figure 4). The ‘bla cker- than-black’ signal, or line blanking (LBL, output of N12), lasts from 72g (through 77g and 00g) to 05g. This corresponds to 58 /is in one line through to 5 /is in the next line. The total duration is therefore 12/is, with the 4 /is sync pulse ‘off- centre’ in the middle. Something similar is required for the field sync. The field sync pulse itself, FSY, lasts from half-lines 590_. . . 594; the equalizing pulses FSE from 585 .. . 589 and from 594 . . . 599; and the field blanking FBL (blacker-than- black) from 585 . . . 624. To be slightly more specific, the sequence is as follows. During the first five half- lines , 585 .. . 589, the output of N19 (FSG) is low . This allows the equalizing pulses EQP from N20 to pass gate N22, and from there through N26 to the output. During the next five half-lines, 590 . . . 594, the output from N18 (field sync, FSY) is high. This field sync pulse is mixed with the equalizing pulses EQP in gate N25, giving the output FSY. Finally, during the third five half-lines, 595 . . . 599, the second set of equal- izing pulses are passed through gates N22 and N26. During this whole period (585 . . . 599) the output of N24 is low, providing the first part of the frame blanking FBL; during the following period (600 . . . 624) gate N13 takes over this frame blanking function. The normal line sync (LSN) is blocked by gate N23 during the field sync sequence. The function END corresponds to the end of each field (half-lines 575 .. . 599), and it can be useful for synchronising external circuits. The video input is connected to N28. Resistors R3, R4 and R5 are a simple digital-to-analog converter which pro- duces the correct video output levels for the various signals: ‘white’ = 100%; ‘black’ = 35% (BLA); ‘blanking’ = 30%iLBL) and FBL); ‘sync’ = 0% (SYP). Character generator The circuits described so far produce basic timebase outputs (from 'A /is to field sync) and all necessary sync pulses. There is also an input for digital video signals. The next step is to produce digits in the desired video format. The height of the characters is deter- mined by the ‘vertical unit’: 4 lines. In figure 5, the input is at line frequency. Two flip-flops (FF7 and FF8) are used as a divide-by-four counter; output Q 1 3 is the ‘vertical unit’. The following three flip-flops (FF9 to FF 1 1 ) form a vertical unit counter, and the six vertical units required (LI . . . L6) can be derived from their outputs. Gates N35 and N36 form a fli p-flop. When this is set, output Qll holds FF7 . . . FF1 1 in the reset condition, so that no digits can be ge nerat ed. Gate N34 produces the signal DST (display start), resetting flip-flop N35/N36. This enables the other flip-flops, but it takes a further four lines for Q13 to change state for the first time, starting the character generation. If the inputs to N34 are connected as shown, the digits will be written at the bottom of the screen. The vertical unit counter counts from L0 to L6. When it switches to L7, flip- flop N35/N36 is set by gate N33. This, in turn, resets and blocks FF7 . . . FF1 1. End of digit. The width of the digits is determined by the horizontal units: 'A /is, 1 /is and 'A /is for tl, t2 and t3 respectively. These units are derived from the time- base generator by part of the circuit shown in figure 6. N56 derives tl from Ql, Q2 and CLK, so 1 1 corresponds to the first Vi /is out of every 4 /is. N57 produces t2, the fol- lowing 1 /is; finally, N58 produces t3, the final Yi /is. After a further 2 /is (the gap between digits), the cycle is re- peated. This total cycle, corresponding to digit-plus-gap, is repeated 16 times for each line, or 1 3 times for the visible portion of each line. These horizontal units tl ... t3 are now combined with the vertical units LI . . . L6 from figure 5 and the seven- 1036 — elektor October 1976 digits on TV segment signals a . . . g to produce the total video output BLA. As an example, segment A is formed as follows. Horizontal units 1 1 . . . t3 are combined in N62, giving a signal over the full width of the digit. Vertical unit LI and seven-segment signal ‘a’ are combined in N59. The outputs from N62 and N59 are then combined in N63 to produce the video output A, corresponding to segment A in the display. Gates N52 and N54, wired into the ‘segment A’ circuit, give a certain ‘finesse’ to the unit . . . The seven- segment decoder used gives a basic ‘6’, that is, the top bar (segment A) is missing. However, a clearer display is obtained when this segment is added. If the A segment is driven whenever the D and G segments are ‘on’, the only difference is that this top bar is added to the ‘6’. Gates N53 and N55 perform a similar function to improve the display of the ‘9’. The digital video output BLA can be connected to the video input in figure 3 (N28) to give white digits on a black background. If black digits on a white background are required, an inverter will have to be connected in series. If both options are required, an exclusive- or gate can be connected in series, with a switch between the other input of this EXOR and ground. In the discussion so far we have simply assumed that seven-segment signals a . . . g are available. Happily, they are not difficult to obtain. The BCD to seven-segment decoder is shown in fig- ure?. The decoder is a 7447 (IC8). Under normal conditions it converts a binary code to a seven segment output. Its out- put is only enabled during the time that digits are being displayed (DPT = dis- play time) and the tim e that the digits are not changing (PLG = parallel load gate). These functions will be explained further on. The ‘lamp-test’ input is connected to S 1 — after all, if an input is available, why not use it? This simply produces an ‘8’ at the output, i.e. all seven segments, so that it gives a quick check of the logic circuits. The display should be 88888888 when this switch is closed. Display generator The eight-digit display is derived from a frequency counter. The circuit (figure 8) is not very sophisticated, since the main purpose is simply to derive eight digits to drive the display. It is simply one example of how to drive the rest of the circuit. The frequency counter consists of eight decade counters ( IC14 . . . IC2 1 ). The input count pulse (CTP) comes from the input gate N67. The input frequency is applied to the input (INP), as one would expect . . . The 50 Hz output from the main timebase (Q10D in figure 2) is divided by 50 in IC12 and IC13 to produce a 1 second output which drives the input gate. During the time that Q18A is low digits on TV elektor October 1976 — 1037 Figure 3, The sync generator. This produces the line and field sync pulses, line and field blanking, and includes a video input. Figure 4. Pulse diagr am s howing the deri- vation of the line sync (LSYI and line blanking (LBL) pulses. Figure 5. The vertical unit counter. This also aroduces the ‘display start' signal corre- ■ponding to the top of the display. Figure 6. The horizontal unit counter and •even-segment to video encoder. Table I. Part of the counting sequence of the two divide-by-eight counters (FF1 . . . FF6). (1 second), the input gate is blo cked and a short output pulse is given at PLG and PLG. These latter outputs block the seven-segment decoder (figure 7) and load the shift register (figure 9), as will be explaine d fur ther on. T oward s the end of the PLG pulse, the END pulse also appears (from figure 3) at the input of N66, producing a reset pulse (RES) for the eight decade counters 1C 14...IC21. A completely separate unit within the display generator is the section shown at the bottom of figure 8. This could also be labelled the ‘display position gener- ator’. The character generator (figure 5) deter- mines the vertical position of the digits: the half-line counter is enabled by the DST signal. However, the horizontal position is still undetermined. The unit is designed to produce a row of 8 digits. Each digit takes 4 /is, so the total display width (including the gaps between the digits!) is 8 x 4 = 32 /is. An exclusive-or gate (N72) is used to derive the ‘display time’ signal (DPT) from the 1038 — elektor October 1976 digits on TV main timebase. This signal lasts 32 /is and it is positioned in the centre of each line. Gate N7 1 derives a signal from the verti- cal time unit counter in the character generator (figure 5). This signal corre- sponds to the total vertical height of the digits. The combination of the horizon- tal display position DPT with the verti- cal display position signal from N71 results in a signal which correspon ds to the exact position of the display: DSC. During this display period, pulse t3 from figure 6 is passed by gate N74. The result is a sequence of pulses which coincide with the end of each digit. This signal is used as ‘clock’ (SRC) for the shift register. This is the next part of the circuit to be discussed. Display memory During the ‘count’ period, the result of the preceding count must be stored somewhere. Furthermore, since there is only or.e character generator, the eight digits in the total display must be presented to this character generator one at a time and at the correct mo- ments. Both of these requirements can be fulfilled by using a shift register as a memory. This shift register (figure 9) uses eight ICs. It actually consists of four separate shift registers running in parallel, one for each binary ‘bit’. The, top shift register (IC22 and IC23) is used for storing the eight ‘least significant bits’ (Bit A) of the eight digits in the displays, so its output is connected to the ‘A’ input of the decoder (figure 7). The remaining three registers are used for bits ‘B’, ‘C’ and ‘D’ respectively. At the end of each count period, the outputs of the eight decade counters in figure 8 correspond to the eight digits required for the display. The Most Significant Digit (i.e. the left-hand one) corresponds to the output of IC2 1 , and so on down the row to the Least Signifi- cant Digit which corresponds to the output of IC14. The display on the TV screen is written from left to right, so the first digit will be the Most Signifi- cant Digit. The correct order to store the digits in the shift register is there- fore: output from IC21 at the extreme right-hand end (the output), and all other outputs in order down the register from right to left. The actual storing of the information into the shift register is controlled by the ‘parallel load gate’ signal PLG (from figure 8). This signal appears just before Figure 7. The binary to seven-segment decoder. The circuit includes display blanking and leading zero blanking. Figure 8. The frequency counter and shift register clock pulse generator. Figure 9. The shift register. the start of each new count. If no further action is taken, the Most Significant Digit will remain at the out- put of the shift registers. This digit will then appear eight times on the screen during the display period. Since this is not the intention, the shift registers must now be set into motion. This is what the ‘shift register clock’ signal is needed for. As discussed in the previous section, the SRC signal consists of a sequence of pulses which coincide with the end of each digit. They are only present during the display period. The shift registers move their information up one position on the trailing edge of each clock pulse. This corresponds to the end of each digit. The results are now as follows. At the beginning of each line of the display period, the Most Significant Digit is present (in binary code) at the output of the shift registers. After the corre- sponding pattern has been displayed, the shift registers move up one position so that the second digit is present at the output. After the pattern for this digit has been displayed, the shift registers advance again, and so on. As the infor- mation for the digits is shifted out at the right-hand end it is fed back in at the left, so that it is not lost. Display blanking The only part of the circuit not yet discussed is the lower part of figure 7 : the display blanking. The output of gate N29 is ‘1’ outside the display time (DPT) and during the time that new information is bein g loaded into the shift registers (PLG). This ’DBL’ signal is inverted by N30 and drives one of the display blanking inputs of the decoder. The result is that all out- puts go to ‘1’ and none of the seven segments can be displayed. Furthermore, flip-flop N31/N32 is reset and the output of N3 1 drives the other display blanking input. Since the DST signal corresponds to the true display time, including the horizontal bound- aries, this flip-flop is reset during each line after the pattern for the last digit has been displayed . The display blanking now remains operative until the flip-flop is set. As soon as the display time is reached during the next line, this overriding reset is removed. However, this does not mean that the flip-flop is automatically set. For this to happen, the RBO output of the decoder must become logic T (note that ‘RBO’ can be used both as input and as output!). This output remains ‘0’ as long as a zero is present at the decoder input, however. The result is that any ‘leading zeroes’ are suppressed: the display blanking remains operative. As soon as a digit is presented to the decoder that is not zero, RBO becomes ‘1’. This sets the flip-flop, and all further digits (including any zeroes) are dis- played until the DPT signal again resets the flip-flop. M 1040 — elektor October 1976 dual voltage regulators In the article 'Integrated Voltage Regulators' (Elektor 11 and 12) positive and negative 1C voltage regulators of both fixed and variable voltage types were discussed. This article is intended as a follow-up and looks at dual regulator ICs (i.e. those that provide both a positive and a negative output). Practical designs are presented for laboratory power supplies providing up to ±30 V at 2 A. Since the vast majority of electronic circuits are designed for a positive supply rail the first 1C voltage regulators were, quite naturally, designed to provide a positive voltage. In particular ICs were designed to provide ‘on-card’ stabilizing for logic circuits. Since the demand for negative voltage regulators was less, these were developed later and fewer types are available (see tables 1 and 2 p. 437 Elektor 12). With the proliferation of operational amplifiers, audio amplifiers using op- amp techniques, analogue comparators and other ICs requiring a positive and negative supply, dual regulator ICs have been introduced. Tracking regulators Most manufacturers of dual regulators use the “tracking regulator’ principle. Basically this means that both the positive and negative halves of the regu- lator use a common reference voltage, and the circuit is so designed that any voltage variations in one of the outputs will be followed by the other output. For example, if the positive supply of a dual regulator is designed to track the negative supply then, should the nega- tive supply go more negative due to temperature drift or load variations, the positive supply will go more positive. This is particularly important in oper- ational amplifier circuits, where the DC conditions in the circuit may be affected by the symmetry of the supply voltages. An example of a dual tracking regulator, the National Semiconductors LM325,is given in figure 1, which shows the internal block diagram of the IC. The negative output voltage is obtained in the usual manner. A negative reference voltage (A) is fed into the non-inverting input of an amplifier (B). This drives the regulator output stage (C) and a voltage is fed back to the inverting input via the potential divider Ra/RB- The amplifier drives the output stage until the output voltage (-15 V in this case) is such that the voltages on the inverting and non- inverting amplifier inputs are almost equal (within the limits determined by the loop gain). The output voltage is 111118 Ra + Rb V OU t = V re f * Ra The positive half of the regulator also has an amplifier and output stage, but in this case the non-inverting input is connected to the 0 V rail while the feed- back is derived from the junction of the two resistors R1 and R2. The amplifier will adjust the positive output voltage until the voltage on its inverting input equals the voltage on its non-inverting input, which means that the voltage at dual voltage regulators elektor October 1976 - 1041 Figure 1. Block diagram of the LM325 dual regulator 1C. Figures 2 and 3. Positive and negative output stages of the LM325 showing the possibilities for external connections. Figure 4. a. Graph showing temperature de- pendence of negative sense voltage, b. Graph showing temperature dependence of positive sense voltage. the junction of R1 and R2 must be zero. This means, for instance, that if R1 = R2 then the positive output volt- age must always equal the negative out- put voltage. If the positive and negative voltage are to be different then R1 and R2 are different. This is the case with the LM327 which provides a +5, —12 V supply. In this case R1 and R2 would be in the ratio 1:2.4. Block D contains protection circuits that a. limit the output current b. switch off the output if the IC becomes too hot (thermal overload). The protection circuits operate on both the negative and positive outputs, so both supplies are well protected against thermal overload and short-circuited outputs. Applications The range of applications for the ICs in the National dual regulator series (LM325 - ±15 V, LM326 - ±12 V, LM327 - +5 V -12 V) become more obvious on studying the internal circuit of the IC, or at any rate the sections that are of interest. Figures 2 and 3 show partial circuits of the positive and negative output stages respectively, together with some possibilities for external circuitry to extend the range of applications. The ringed numbers corre- spond to the pin connections of the IC. 1042 — elektor October 1976 dual voltage regulators Internal current limit Resistor R5 in the emitter lead of T5 is the internal current sensing resistor for the positive regulator. With pins 1 , 2 and 3 of the IC connected together as shown in figure 2a, T8 will start to con- duct as soon as the voltage drop across R5 reaches the base-emitter voltage of T8. This limits the base current into T4 and hence limits the output current. The output current limit is given by: llim (amps) = Where V sense is the base-emitter voltage of T8 in volts and 2.25 is the value of R5 in ohms. The current limiting func- tion for the negative supply is per- formed by R26 and T27 in figure 3a. The value of V sense decreases with increasing temperature, so at high tem- peratures the current limit will operate at a lower current. Graphs of V sense versus temperature are given for the negative regulator in figure 4a, and for the positive regulator in figure 4b. Fig- ures 6a and 6b show how the onset of current limiting varies with temperature. External current limit If the short between pins 1 and 2 of the IC is replaced by a resistor as in fig- ure 2b then the current limit can be controlled externally. When the voltage drop across R S ense reaches V sense then T1 1 will turn on, limiting the base drive to T4. It is, of course, impossible to obtain an output current greater than that determined by the internal current limit, since this is still operative. Rsense must therefore always be greater than R5. The output limit current in this case is given by: The external current limit function for the negative regulator is performed by T39. The values for V sense may again be obtained from figures 4a and 4b. Increased output current Like many other IC regulators, the out- put current of the LM325 series can be increased by adding an external power transistor. This is shown in figures 2c and 3c. Since the external transistor is not protected by the internal current limit it is essential to use an external current limit resistor. This is calculated in the same manner as for the current limit resistors in figures 2b and 3b, but there are now no restrictions on its value due to the internal current limit. Since the IC is now supplying only the base current for the external transistor then (if the external transistor has suf- ficient gain) several amps can be drawn Figure 5. The most basic application of the LM325. Figure 6. a. Graph showing onset of negative output current limiting at different tempera- b. Graph showing onset of positive output current limiting at different temperatures. Figure 7. LM325 with external power transis- tors to increase the output current capability. Figure 8. Functional block diagram of the Elektor PSU 76. Figure 9. Prestabilizer section of the PSU 76. dual voltage regulators elektor October 1976 - 1043 before the internal current limit oper- ates. Practical circuits The simplest circuit for a ±15 V regu- lator using the LM325 is given in fig- ure 5. Pins 1, 2, 3 and 5, 6, 8 are joined as in figures 2a and 3a, so only the internal current limit is operative. The decoupling capacitors Cl, C2, C4, and C5 improve ripple rejection and sup- press any tendency to RF instability. They should be tantalum types. C3 suppresses noise generated by the internal voltage reference, and is only necessary if a very low noise level is required at the output. ±15 V 2 A regulator The complete circuit of a ±15 V regu- lator with 2 A output current capability is given in figure 7. The sensing resistors can be chosen to give a current limit anywhere between 0 and 2 A. The popular 2N3055 power transistors are used as the output devices. It should be noted that 2N3055s are manufactured by two different processes, the planar process and the diffusion process. Those made by the planar method have a higher cutoff frequency (fj) due to lower internal capacitances. These are preferable in this application as they introduce less phase shift into the cir- cuit, and the danger of RF instability is consequently less. If 2N3055s with an fj of less than 1 MHz are used then additional phase compensation may be required. C2 and C4 should be increased to 50 n or greater and a 100 p capacitor may be connected between pins 8 and Elektor PSU 76 The LM325, 326 and 327 can supply only fixed voltages, but for laboratory use a variable supply is much more versatile. The Elektor PSU 76 is in- tended for use in laboratory or work- shop and can supply independently variable positive and negative voltages from 0 to 15V at currents of up to 1.2 A. A block diagram of the PSU 76 is given in figure 8. The circuit is slightly un- usual in that it incorporates, between the unregulated supply and the regu- lator, a prestabilizer stage. This takes the unregulated ±24 volt input and provides a prestabilized ±19 V output to the stabilizer. This means that the stabilizer does not have to cope with large line voltage variations and can be relatively simple. The circuit of the prestabilizer is given in figure 9. The heart of this circuit is a Silicon General IC regulator type SG3501T. This will provide adjustable positive and negative output voltages that can be varied by PI. The outputs track so they are not (unfortunately) independently adjustable. The output current of the IC is increased by T1 and T2 while R4 and R5 set the current limit to about 1.2 A. There is thus no need for current limiting in the output stabilizer. Capacitors C3 and C4 sup- press any tendency to HF oscillation, and they should be tantalum types. This also applies to C7 and C8. Output Stabilizer Figures 1 0 and 1 1 give the circuits of the positive and negative output stabil- izers respectively. These are constructed entirely from discrete components and are of fairly conventional design, con- sisting of a differential amplifier, driver and series pass transistors. The only slightly unusual points in the circuits are the arrangements made to allow the out- put to be adjusted down to zero. In a more conventional design a positive reference would be applied to the base of T3, which would be balanced by a feedback voltage from the output to the base of T4. With such a design it is not possible to obtain an output less than the reference voltage. In this design the base of T3 is grounded and a negative reference voltage is applied to the emitter resistor (R7) of the differential amplifier. The reference voltage is derived from the unregulated negative 1044 - elektor October 1976 dual voltage regulators 10 1N4001 supply (point D in figure 9) and is stabilized by D4. Instead of the usual potentiometer to vary the feedback voltage and hence the output, the PSU 76 uses a potentiometer connected as a variable resistor in series with a con- stant current source T7. The current supplied by T7 is adjusted by P3 to about 7 or 8 mA, so that with P2 at maximum resistance the voltage on the base of T4 is slightly negative. The negative output regulator (fig- ure 1 1) is simply a minor image of the positive regulator, so the foregoing remarks apply to this also, except that negative becomes positive and vice versa. A printed circuit board and com- ponent layout for this power supply are given in figures 12 and 13. ±30 V 2 A regulator If the facility for independent adjust- ment of the positive and negative out- put voltages is not required then a much simpler circuit may be designed. Fig- ure 14 shows the circuit of a ±30 V 2 A regulator based on the Raytheon RC4149. This IC will supply output voltages continuously variable between ±50 mV and ±30 V. The maximum output current of the IC is 150 mA for the DIL package and 200 mA for the TK package (metal can similar to TO-66). The IC has thermal protection that shuts down the outputs at a chip temperature of +175 C. In the circuit of figure 14 the output current capability of the IC is increased Parts list for figures 9, 10, 11, 12 and 13 Resistors: R1 = 1 k R2.R3 = 75 O R4.R5 = 0.47 n, 2 W R6.R11 =270 0 R7.R12 ■ 1 k5 R8.R13 ■ 470 n, 0.5 W R9.R14 = 560 O R10.R15 ■ 470 PI = 50 k trimpot P2.P4 * 2k5 lin. P3.P5 = 500 Jt trimpot Capacitors: Cl ,C2 * 4700 n, 35 V C3,C4 = 4(i7, 3 V, tantalum C5.C6 = 10 n C7,C8 = 10(i. 25 V, tantalum C9,C14 = 100p, 25 V C10.C15 = 220 m. 25 V C11.C16 = 100m,12V C12.C17 = 100 n C13,C18 = 100m. 16 V Semiconductors: IC1 =SG3501T (Silicon General) T1 = BD 242, 2N4919 T2 = BD 241, 2N4922 T3.T4.T7 = MPS A18, BC 182 B T5 = BC 160, 2N2561 T6 = TIP 3055 T8,T9,T12 = BC 307 B, MPS A70 T10 = BC 140, 2N1711 Til = TIP 2955 D1 = LED D2,D6 = BY 127 (50 V/5 A) D3.D7 = 1N4001 (80 V/3,2 A) B1 = B80C3200 D4.D8 = zener 8V2, 400 mW D5.D9 = zener 5V6, 250 mW Various items: T r = transformer 2 x 16 V, 2 A Ml ,M2 = panel meters, 15 V f.s.d. f = 0.5 A fuse, slow blow SI = mains switch Figure 10. Positive output regulator of the PSU 76. Figure 11. Negative output regulator of the PSU 76. Figures 12 and 13. Component layout and p.c. board for PSU 76 (EPS 9004). by T1 and T2, and external current limiting is provided by T3 and T4 in conjunction with current sensing re- sistors R3 and R4. The output voltage is adjusted by PI. R5 determines the reference current fed into PI and hence the output voltage range (scale factor) over which PI is effective. 71k5 is the correct value for the output voltage dual voltage regulators elektor October 1976 — 1047 Figure 14. ±30 V 2 A regulator. Outputs are not independently adjustable in this circuit. Figures 15 and 16. Component layout and p.c. board for ± 30 V 2 A regulator (EPS 90051. Figure 17. Pinouts of the ICs described in this article. Parts list for figures 14 and 16 Resistors: R1.R2-47H R3.R4 ■ 0.33 ft/2W R5 ■ 71 k5 R6 - 3k3. 1 W PI - 100 k lin. P2-47 k lin. Capacitors: C1.C2- 4700 m. 35 V C3.C4 > 1 n C5.C6 = 100 m. 35 V Semiconductors : IC1 = RC4194 (Raytheon) T1 = TIP2955 T2 = TIP3055 T3.T4 = BC140-10, 2N171 1 D1 = LED B1 = B80C5000 (80 V, 5 A) T r = mains transformer, 2 x 22 V/2 A range 50 mV-30 V. If this is difficult to obtain then a 68 k may be used instead, but the output voltage with PI at max will then not be exactly 30 V. Some adjustment of the output voltages relative to one another is possible with the balance control P2, but its inclusion is not really recommended unless dif- ferent positive and negative output volt- ages are really necessary. A switch is fitted since P2 must not be left in cir- cuit when the positive and negative out- puts are to be equal, as it will affect the balance even in its maximum position. With the value given P2 is effective only in the lower voltage ranges (up to about 1 5 V). For use above 1 5 V its value must be increased considerably, and this introduces further complications since additional decoupling is then necessary. A printed circuit board and component layout for the ±30 V 2 A regulator are given in figures 1 5 and 1 6. Note that the board is designed for the TK package version of the IC. Figure 17 gives the pinouts of all the ICs described in this article. Constructional points The most important constructional point is that all the power transistors must be adequately cooled. Remember that a stabilized supply is effectively a class A amplifier. Each of the devices in the 30 V regulator may have to dissipate over 70 W when the output is short- circuited, so the heatsinks should have a thermal resistance of less than 1°C/W if the temperature is not to rise more then 70° or so above ambient. In the PSU 76 design the dissipation is split between the power transistors in the prestabilizer and those in the output stage. The worst case dissipation in the output transistors occurs when the unit is supplying low voltages at 1 .2 A, and is about 22 W. The worst case dissipation in the prestabilizer transistors occurs when the output is shorted with the output voltage set to maximum. The dissipation in each transistor is then about 28 W. Heatsinks with a 3°C/W thermal resistance would be adequate in this power supply. Use caution when selecting the power transformer. The output voltage should not exceed 2 x 22V (2 x 22 V is a good value). It is advisable to measure the voltage between the IC case con- nection and pin 5, before the IC is installed on the p.c. board. This voltage must not be more than 35 V DC, if it is, the IC will be damaged. A good safety margin is a good idea. Literature: National Semiconductor, Raytheon and Silicon General data sheets and appli- cation notes. M 1048 — elektor October 1976 (to (UM)® CD©MS(n) Loud hailers are used wherever people need to make themselves heard over a large distance. The design described here is meant for use in cars and thus derives its power from the car battery. This means that the maximum voltage available is only 12 Volts, so some unconventional circuits are required to produce sufficient audio output power. A symmetrical output stage using a transformer is used to feed a 4 ohm loudspeaker, which results in a 16 to 1 power step-up when compared with a conventional push-pull arrangement. The amplifier operates in class C, which is a bit unusual for audio use. To reduce the effects of (class C) crossover distortion a high frequency bias is superimposed on the input audio signal. The effect of these somewhat unusual features are described in the following paragraphs. the LOUD mouth lower. This means that for a 12 volt I power supply and a 4 ohm loudspeaker the theoretical maximum output power j (not including losses) would be approxi- mately 4.5 W, obviously on the low side for a ‘loud’ hailing system. Much more power for a given supply j voltage can be delivered by a bridge- , type output stage. This consists of two identical output stages driven in anti- I phase. In this way the voltage swing is doubled, which results in a 4 fold power increase (Pmax approximating V 2 /2 Rl). Under the same given con- ditions this arrangement will yield us | a maximum output power of about I 18 W. In the final design, the power j available from the output stage is stepped up by a further factor of 4 by j using a 2 to 1 load matching trans- < former. P ma x is now approximately j V 2 /Vi R l, which (theoretically) would 1 give 72 W into a 4 ohm load at 12 V. Allowing for unavoidable losses, the actual output will be about 40 W. The signal delivered by this final stage will not be exactly ‘hi-fi’. The main objective with this design was to help a ‘soft’ speaker to become a ‘loud’ speaker. High fidelity is of secondary importance. In spite of the relatively poor audio quality, however, good intelligibility is maintained. Main amplifier The main amplifier circuit is shown in figure 1 . There are two inputs, one for I speech, one for music, with mixing controls PI and P2. The input signal is passed on to a phase splitter that produces the in-phase signal (at the I splitter emitter) and the anti-phase signal (at the collector) required for the symmetrical pushpull stage. To increase the output power even further, an output transformer is used. The function of this output transformer can be explained as follows. If the amplifier is fully driven, at one ‘end’ of the output swing T5 will be fully con- ductive and T6 will be cut off. At that instant, the current flowing through The primary power supply is limited to the 12 volts derived from the car battery. It would, theoretically, be possible to have this voltage stepped up by some sort of converter device which would enable a higher power output level to be obtained with a given loud- speaker impedance, but in practice this leads to poor efficiency and great expense. A more practical approach is required. First, let us consider the problem in greater detail. The maximum power supplied by a single ended pushpull stage is roughly calculated from the following rule-of-thumb equation: Pmax = V 2 /8 Rl in which V stand for the power supply voltage and Rl for the load impedance. This formula completely disregards all losses in the output stage. The actual maximum output power will be even L 3ie LOUD mouth elektor October 1976 - 1049 transformer winding W1 will set up a corresponding maximum output The HF bias voltage across this winding of 12 V. The power will then be approximately emf induced in the opposite trans- „ _ U 2 _ 17 2 ~ 77 w » t . H The output stage operates in class C, former winding will also be 12 V, which max Rl 4 ~ • s s a e so t j, e drive signal must reach a certain results in 24 volts across the entire earlier, the inevitable losses will reduce level before the output responds. The transformer and, therefore, across the the maximum output power in practice advantage of class C operation is the loudspeaker terminals. This is the peak to about 40 W. relative immunity to temperature flue- swing for a half-period of the output To cut down distortion, resistor R21 tuations. However, class C also has a signal. The r.m.s. value is 0.7 x 24 V, provides some degree of negative feed- major drawback: if no special pre- which is approximately 17 V. The back. cautions are taken, the ‘dead zone’ the LOUD mouth elektor October 1976 1051 inherent to this type of operation will cause objectionable crossover distortion In this design the distortion was reduced by superimposing an HF bias signal onto the input audio. This HF bias consists of nothing more than a 30 kHz square wave signal. It is generated by an astable (T9, T10). The effects of this HF bias can be better explained from the graphs shown in figure 2. Figure 2a shows a given input audio signal. The central dead zone in which Ihere is no output response is shown in figure 2b, the resultant output accord- ing to 2b' clearly indicating severe cross- over distortion. Figure 2c shows the effect of a square wave superimposed upon the original input signal. The out- put signal, which also has this square wave superimposed on it, would fill the area between the dashed lines in fig- ure c\ However, after filtering, the out- put signal becomes equal to the average value, which is shown as a bold line in figure c'. This curve demonstrates a more continuous transition over the dead zone, resulting in a much lower distortion. When the HF bias amplitude is in- creased, as shown in figure 2d, the smoothed output signal will be as indicated by the bold line in 2d'. Evi- dently, crossover conditions are deter- mined by the HF bias amplitude and the offset ‘A’ which in turn depends on the width of the dead zone. This width may be affected by temperature changes, but this has little effect on the audible dis- tortion. The transition zone ‘B’ depends directly on the HF bias amplitude, which in turn depends on the power supply voltage. However, 2d' indicates that fluctuations in the supply voltage and, consequently, fluctuations in the width of zone ‘B’ will not audibly affect the distortion in the output signal. P3 is used to set the HF bias amplitude. The microphone preamplifier The sensitivity (gain) of the main ampli- fier, shown in figure 1 , is not very high. For this reason a preamplifier stage must be added if a dynamic microphone is to be used. The circuit for a suitable preamp is shown in figure 3. It is included on the printed circuit board. The discrete transistor stage (Tl) acts both as an impedance matching device and a low noise amplifier. Since the noise characteristics of the preamplifier output stage, a 741 opamp, are not all too favorable, a satisfactory signal-to- noise figure could not be obtained with- out the help of this additional transistor. The overall gain now becomes so high that it will readily lead to clipping of the preamplifier output signal. In prac- tice, this is usually not so serious for speech: the intelligibility of spoken messages is still quite good, and it has the advantage that the average output power of the system is greatly increased. However, if the distortion is too objec- tionable the value of R8 can be de- creased, reducing the sensitivity to a suitable level. On the other hand, if the gain is too low then R8 can be increased 1052 elektor October 1976 LOUD mouth improved current : improved current source The basic circuit of a current source is shown in figure 1 . The base-to-emitter potential for the source transistor T1 is derived from the *+l’ power supply terminal through the to a suitable value. The preamplifier is meant for 50 kft microphones, but also works quite well with 500 ohm mikes. Some practical advice Figure 4 shows the printed circuit board and component layout. The HF bias is set with P3. Connect an ammeter in the power supply line and adjust P3 so that under no-signal conditions the current is about 300 to 400 mA. To prevent any mishaps when the equip- ment is being connected to the car battery it is recommended to insert a fuse of approximately 5 A in the power supply line. The power transistors T5, T6 and the drivers T4, T7 require heat sinks. Cooling fins will suffice for T4 and T7; T5 and T6 must be mounted on a heat sink with a thermal resistance of 3°C/W or less. There is sufficient room on the p.c.b. for all of these sinks. T r can be a standard mains transformer with two 12 V, 3 A secondaries. The primary is not used, but since it will develop an uncomfortably high voltage its terminals should be well insulated. The circuit is designed for 4 ohm loud- speakers. However, if 40411 transistors are used for T5 and T6, a 2 ohm load is permissable. In that case the maximum output power will increase to some 80 W. potential divider Rl, Dl, D2. The T1 collector current is approximately 600 .. . 700 -milliamps R 2 where R2 is in ohms. Minor fluctuations in the ‘+1’ voltages I affect the T1 collector current via the I differential resistance of Dl and D2. This can, of course, be prevented by using a zener diode to stabilise the ‘+1’ voltage. An alternative method is to add a resistor R3 from the ‘+1’ terminal to the I where V is the voltage *+l’, the T1 col- I lector current will remain constant in I spite of supply voltage fluctuations. H | advertisement elektor October 1976 1059 All mail to: Henry's Radio 303 Edgware Rd. London W2 LONDON W2 : 404/6 Edgware Road. Tel: 01-402 8381 LONDON W1 : (lower sales floor) 231 Tottenham Court Road. Tel: 01-636 6681 SfiaiMs llV! Capacitive discharge elecfronic ignilion kif Smoother running Instant all-weather starting Continual peak performance Longer coil/battery/plug life Improved acceleration/top speeds Up to 20% better fuel consumption PRICES INCLUDE VAT, POST AND PACKING. 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