902 - elektor September 1975 publisher’s notices ELEKTOP Volume 1 — number 6 Many Elektor circuits are accompanied by designs for printed circuits. For those who do not feel inclined to etch their own printed circuit boards, a number of these designs are also available as ready-etched and predrilled boards. These boards can be ordered from our Canterbury office. Payment, including £ 0.1 5 p & p, must be in advance. Delivery time is approximately three weeks. Bank account number: A/C No. 11014587, sorting code 40-16-11 Midland Bank Ltd, Canterbury. circuit number austereo 3-watt amplifier HB1 1 austereo power supply HB12 austereo control amplifier HB13 austereo disc preamp HB14 universal frequency reference HD4 distortion meter 1437 a/d converter 1443 tap sensor 1457 minidrum gyrator 1465A minidrum mixer/preamp 1465B minidrum noise 1465C beetle 1492 equa amplifier 1499 electronic loudspeaker 1527 mostap 1 540 car power supply 1 563 digital rev counter (control p.c.b. only!) 1590 car anti-theft alarm 1 592 mos clock 531 4 clock circuit 1 607A mos clock 531 4 display board 1 607B mos dock timebase 1 620 minidrum tap 1621 A minidrum ruffle circuit 1 621 B automatic bassdrum 1621C microdrum 1 661 aerial amplifier 1668 coilless receiver for MW and LW 31 66 tap preamp 4003 twin minitron display 4029-1 twin led display 4029-2 twin decade counter 4029-3 recip-riaa 4039 disc preamp 761 31 4040A maxi display 4409 dil-led probe 5027 A+B big ben 95 5028 compressor 601 9A tv sound 6025 tup/tun tester 9076 tup/tun tester front panel 9076/2A p.c.b. and wiring tester 9106 rhythm generator M252 9110 7400 siren 9119 CA3090AQ stereo dekoder 91 26 kitchen timer 9147 capacitance meter 9183 issue price 5 1.10 5 0.55 5 1.50 5 085 5 1.10 1 1.65 3 0.90 1 0.60 2 080 2 0.55 2 1 .05 4 2.20 1 120 2 0.50 2 1 .05 4 125 1 0.55 4 1.40 1 1.15 1 085 4 0.70 2 0.70 3 1.10 3 085 2 095 1 025 5 080 4 1.80 2 1.40 2 1.40 2 1.40 2 0.50 3 095 2 1.50 2 1.85 2 125 3 120 2 1.40 4 1.70 4 190 5 0.55 5 080 5 0.75 5 080 5 0.75 5 0.75 (25) (25) (25) ( 8) ( 8) (251 (25) (25) i 8) (25) (25) (25) ( 8) ( 8 ) 125) 125) (25) ( 8) ( 8) ( 8) (25) (25) (25) ( 8) ( 8) NEW: edwin amplifier miniature amplifier light dimmer versatile digital clock car clock (2 boards) car clock front panel (transparent red plastic) number issue price % VAT 97-536 6 1.20 (25) 1486 6 0.55 (25) 1487 6 0.45 ( 8) 4414A 6 1.10 ( 8) 7036 6 1.75 ( 8) 7036-3 6 0.90 ( 8) Editor Deputy editor Art editor Drawing office Subscriptions W. van der Horst P. Holmes C. Sinke L. Martin Mrs. A. van Meyel UK. Staff: Editorial : T. Emmens Advertising : P. Appleyard Editorial offices, administration and advertising: 6 Stour Street, Canterbury CT1 2XZ. Tel. Canterbury (0227) - 54430. Telex: 965504. Elektor has been published every two months until August 1975; it now appears monthly. Copies can be ordered from our Canterbury office. The subscription rate for 1975 is £ 3.60 (incl. p & p); the first issue (Nov/Dec 1974) will be included in this at no additional cost. Single copies: £ 0.35 (not incl. p & p). Subscription rates (airmail): Australia/New Zealand European countries outside UK USA All other countries 8 issues £ 7.20 8 issues £ 5.20 8 issues £ 6.25 8 issues £ 6.40 Subscribers are requested to notify a change of address four weeks in advance and to return envelope bearing previous address. Members of the technical staff will be available to answer technical queries (relating to articles published in Elektor) by telephone on Mondays from 14.00 to 16.30. Letters should be addressed to the department concerned: TQ • Technical Queries; ADV = Advertise- ments; SUB “ Subscriptions; ADM ■ Administration; ED = Editorial (articles submitted for publication etc.); EPS = Elektor printed circuit board service. The circuits published are for domestic use only. The submission of designs or articles to Elektor implies permission to the publishers to alter and translate the text and design, and to use the contents in other Elektor publications and activities. The publishers cannot guarantee to return any material submitted to All drawings, photographs, printed circuit boards and articles published in Elektor are copyright and may not be reproduced or imitated in whole or part without prior written permission of the publishers. All prices include VAT at the rate shown in brackets. Copyright © 1975 Elektor publishers Ltd — Canterbury. Printed in the Netherlands. elektor September 1975 — 903 selektor 905 edwin amplifier 910 T>*s a a design for a high-quality 40 W audio amplifier based on an earlier 20 W design. The amplifier embodies nee unus-ai design features and the construction is problem-free. miniature amplifier 917 The orcuit Mill operate from a 4.5 V battery and can be used to amplify the output of a crystal pickup to drive a sma* loudspeaker or headphones. The circuit is not outstanding for its power or quality, but it is simple and ratable. versatile digital clock 918 On» 90 dB. elektor September 1975 — 911 912 — elektor September 1975 The output stage differs from the con- figuration shown in figure 1 because it comprises two NPN transistors of the same type and not a complementary pair. To maintain symmetrical operation of the output stage D 1 is included across R18. This simulates the base-emitter junction which would be present across R18 if the configuration of figure 1 has been used. The values of R17, R18 and R 1 9 are low ( 1 0 fl) to reduce cross- over distortion. Overall negative feedback is applied from the output to the emitter of T2. The inclusion of C3 means, that 100% d.c. feedback is applied, which stabilises the d.c. operating point of the output at around half supply voltage over a wide range of supply voltages without the need for adjustment potentiometers. odwin amplifier elektor September 1975 — 913 The a.c. gain of the amplifier is, of course, given by * _ Vout _ Rio + Rs V Vjn R S ' It is worth noting the effect of the com- bination R7, C5 on the operation of the amplifier. Some amplifiers, when used with an unstabilised supply, display ripple on the peaks of the waveform when driven to clipping. This is elimin- ated by R7 and C5 as follows. When the amplifier is being driven, current flows through R7 and the voltage on C5 is always below the ripple ‘troughs’ on the supply. The drive voltage available from T3 is limited to the voltage on C5 and the output of the amplifier can never swing into the ripple region of the supply voltage. R7 also limits the current through T3 in the event of an overload. Overload protection The protection circuit is designed to prevent excessive current peaks from occurring during signal overloads or short-circuiting of the output. The pro- tection circuit consists of transistors T5 and T6. Their base bias is set such that under normal operating conditions the voltage across R20 and R21 is insuf- ficient to turn them on. In the event of excessive output current flowing in R20 or R21, due to a signal overload or a short-circuited output, the voltage across these resistors is sufficient to cause T5 or T6 to conduct. This reduces the drive voltage to the output stage and there- fore limits the output current, thus protecting the amplifier. Power supply A stabilised power supply is unnecessary with the Edwin amplifier, as its perform- ance will not be significantly improved. A simple unregulated supply is quite adequate and two suitable circuits are given in figure 3. Figure 3a shows a supply using a normal full-wave bridge rectifier, whilst figure 3b shows a full- wave rectifier with a centre-tapped trans- former. The component values and specification for supplies suitable for 20, 35 and 40 W versions of the amplifier are given in table 1. Of course any suitable trans- former may be used, there is no need to adhere to the exact voltages specified. Figure 4 gives the output power available versus transformer secondary voltage. The only points to watch are that the current rating of the transformer is adequate for the required output power, that the voltage rating of the smoothing capacitor is sufficient and that the RMS secondary voltage of the trans- former does not exceed 33 V on load, otherwise the voltage rating of the tran- sistors may be exceeded. Over the range of supply voltages given in figure 4 nothing need be changed in the amplifier as the operating point is self-adjusting. Performance figures The performance figures, as measured on the 35 W prototype of the amplifier are summarised in table II and displayed graphically in figures 5, 6, 7, and 8. As can be seen they are quite exceptional. Among the outstanding features are the large power bandwidth, good signal to noise ratio, immunity to transients, low distortion and absolute stability, even with large capacitive loads. Figure 9 shows the printed circuit board and component layout of the amplifier. Table I Po max v tr t (A) L ci Power (R|_ = 4 Ohm) RMS figure 3b figure 3a supply 1 \ / 1 working no-load \ Mono 1 voltage voltage Stereo Stereo Mono Stereo (V) (V) 42 33 1,1 2,2 4,5 60 46,5 35 30 1 2 4 2500 5000 50 42,5 21 24 0.8 1,5 3 40 34 914 - elektor September 1975 edwin amplifier elektor September 1975 - 915 Figure 9. Printed circuit board and component Components list for figures 2 and 9 Semiconductors: T1.T2 = BC 107, BC 171 T4,T5 = BC 108, BC 148 T3,T8= BD 138 T6= BC 178. BC 158 T7 = BD 137 T9.T10 = 2N3055, BD 130 D1 = BY 127 n VsM 916 — elektor September 1975 Figure 10. Heatsink details for the driver and output transistors. The driver transistors are mounted on the board, with a cooling fin as detailed in figure 10a. The output transistors are mounted on a separate extruded alu- minium heatsink, details of which are given in figure 10b and the associated table. Most manufacturers of heatsinks will have something similar to this in their range. If resistors R20 and R2 1 are not readily obtainable they may be wound from suitable resistance wire. Alternatively wire eight 1 £2 0.25 W resistors in parallel, there is plenty of space on the board to mount them vertically (figure 1 1). Concluding remarks Whilst the Edwin amplifier meets an exacting specification this is no reason to recommend its construction by the Hi-Fi enthusiast. There are many other designs with similar performance. What makes the amplifier eminently suitable for the amateur is its problem-free con- struction and virtual (electrical) inde- ^ fc structibilitv i _^^^^__^^^^^_^_M Table II Performance figures of 35 W version Maximum output power 35 W (4 £2);20W (8 O) f = 1 kHz, THD = 1 % 45 W (4 £2); 27 W (8 £2) THD = 1 0%v Efficiency >60% f = 1 kHz; P„ = 35 W Load impedance 0 ... 00 (Maximum power into 4 £2) Overload protection Proof against long duration short-circuit Maximum capacitive load >100 HF (1) Sensitivity «1 V RMS f - 1 kHz, P 0 « 35 W Input impedance as 45 k£2 Distortion P 0 ■= 0 ... 30 W 0,1% f = 1 kHz 0.2% f- 30 Hz 0,3% f = 10 kHz Frequency response 25 Hz... 1,2 MHz (— 3dB) 40 Hz... 1,0 MHz (-1 dB) Vj n - 245 mV Power bandwidth >100 kHz (—3 dB) Noise rejection 73 dB input open-circuit 93 dB input short-circuit Signal to noise ratio 95 dB input open-circuit >105 dB input short-circuit Feedback factor as 36 dB Stability unconditional miniature amplifier elektor September 1975 — 917 The input and driver stages T1 and T2 operate as voltage amplifiers. The out- put stage, T3 and T4, operates in class B to achieve long battery life. D.C. feed- back is provided by means of R3 and A.C. feedback by means of R3, R4 and C2. This defines the gain, stabilises the operating point and increases the input impedance. The biassing of T1 is critical and the values for R1 and R2 must be adhered to. Should the circuit fail to operate cor- rectly the D.C. conditions may be checked at the base of T3 and T4 and the junction of R6 and R7. If 25 ohm loudspeakers are difficult to obtain, then 8 or 1 5 ohm types may be used instead. In that case R6 and R7 should be replaced by wire links. As can be seen from figure 2 the p.c. board is extremely miniature and finding space in the record player cabi- net should be no problem. To improve loudspeaker efficiency the loudspeaker cabinet should be as large as possible. H Figure 1. The very simple amplifier circuit. Figure 2. Layout of match-box siza printad- circuit board. 918 — elektor September 1975 o 2^* agSs»Ss^»- oO° *• Elektor has previously published designs for ‘one-chip’ digital clocks, with both mains and crystal reference frequencies. Whilst ICs such as the MM5314 are excellent for simple timekeeping, they have certain disadvantages. Since the output to the display is multiplexed the time output of the clock is not easily accessible in a parallel form. This means that the clock is unsuitable for driving time-controlled devices such as alarms, calendars, central heating programming, automatic recording of radio pro- grammes or other systems. The clock described in this article is based on TTL circuitry and is eminently suitable for control systems. The time is avail- able as a BCD coded output, and clock pulse trains with rates varying from one a second to one a day are obtainable. Many constructors will probably have some of the ICs in their ‘junk box’. The complete circuit of the clock (ex- cluding power supply) is given in fig- ure 1. The basic operation is quite simple. With all the switches in the positions shown the clock runs nor- mally. The 50 Hz input is rectified by Dl, clamped to 4.7 V by D2 and then fed into the NAND Schmitt trigger ST1 . A 50 Hz square wave suitable for driving TTL appears at the output of ST1 and is fed to IC10 which is connected as a divide-by-five counter. Asymmetric 10 Hz pulses are available at the ‘D’ out- put of IC10. These pulses are fed to IC9, which is connected as a divide-by- 10 counter. A symmetrical 1 Hz square wave is available at output ‘A’ of this IC. The 1 Hz pulses are fed to IC6, which is connected as a BCD decade counter. This counts seconds from 0 to 10 and the BCD output may be decoded for display using a 7447. The ‘D’ output of IC6 produces one pulse every ten sec- onds, and this is fed to IC5, which is connected as a divide-by-6 counter. This counts tens of seconds from 0 to 6. When the tens of seconds count reaches 6 (Le. the seconds display changes from 59 to 60) the BCD output of IC5 is 0110, that is to say the ‘B’ and ‘C’ out- puts of the IC are both ‘1’. These out- puts are connected to the Reset 0 in- puts, so that when the count reaches 6 ICS is reset instantaneously, and the 6 display is never seen. One pulse per minute is obtained from the ‘C’ output of IC5, and this is fed through N2 and N1 to IC4, which is again connected as a BCD decade coun- ter. The time-setting circuits around N 1 and N2 will be discussed later. Like ICS, IC3 is connected as a divide- by-6 counter, so that it counts tens of minutes. Counting of the hours is slightly more complicated. Since the clock is a 24 hour design, the hours counter (IC2) must count up to 10 twice, then reset at 4 on the third count sequence (i.e. when the hours count reaches 24). Since the tens of hours counter only counts to 2 a counter is made up from two JK flip- flops (7473) instead of using a 7490. Resetting is accomplished as follows: During the first 0-10 count of IC2 the Q outputs of FF1 and FF2 are low. When the ‘D’ output of IC2 goes low on the tenth count the Q output of FF1 goes high. At the end of the second count sequence the Q output of FF1 goes low and the Q output of FF2 goes high. The Q output of FF2 and the ‘C’ output of IC2 are connected to the Reset 0 inputs of IC2, so that when IC2 reaches 4 in its third count sequence it is reset. However FF2 cannot similarly be reset as it has no gating on the clear input. This difficulty is overcome by feeding the ‘B’ output of IC2 to the clear input of FF2 via Cl and R3. On count 4 of IC2 the ‘B’ output goes low, feeding a momentary reset pulse to FF2. Of course this occurs at count 8 also, and during the first and second count sequences. However, it is only during the third count sequence that the Q output of FF1 is high anyway, so these earlier reset pulses do not matter, since the flipflop is reset already. The capacitive coupling (Cl, R3) is necessary to ensure that only a short reset pulse is provided. If direct coup- ling were used then the clear input would be held low on count 1 0 during the second count sequence, and the Q output of FF2 could not go high. Provision of 'tick' It will be noted that IC9 is connected differently from the other divide-by- 10 counters (IC2, IC4 and IC6). This is because a BCD output is required from the other counters. IC9 is connected to give a symmetrical square-wave output, as a convenient simulated ‘tick’, and this happens to sound better with a 1 : 1 mark -space ratio. Time-setting Three time-setting switches are pro- vided. Two to make the clock advance at a fast rate, and one to stop the clock. This is useful because the clock can be set to a particular time, stopped, then the stop button can be released exactly on the time signal from radio or tele- phone. It is also handy if the clock is accidentally advanced too far as it saves going all the way ‘round the dial’. Gating for the time-setting is provided by a 7400 (IC7) plus the spare half of the 7413 Schmitt trigger (%IC8). The operation is as follows: when S2 is in the position shown in figure 2a the set-reset flipflop N3/N4 is reset, so the output of N3 is high and the output of N4 is low. This means that the output of ST2 is high. Pulses from output ‘C’ of Figure 1. Circuit diagram of the clock. The printed circuit board does not indude the dis- play and its associated decoder /drivers. Figure 2a. Logic levels at NAND gates for normal timekeeping. Figure 2b. Logic leve ls at NAND gates for time-setting. versatile digital clock elektor September 1975 - 921 ICS are thus transferred through N2 and N 1 . When S2 is changed over (figure 2b) the flipflop is set. The output of N3 is low and the output of N4 is high. The output of N2 therefore goes high. 1 Hz or 10 Hz pulses (depending on position of SI) are now transferred through ST2 and N 1 to the input of IC4. The clock will therefore count at the rate of one minute per second or 10 minutes per second. As an alternative to the 10 Hz rate, 50 Hz pulses may be used. This rate is useful only for setting the hours rapidly. The flipflop is necessary to suppress contact bounce on S2. The flipflop is set (or reset) when the switch initially makes contact on being changed over. Subsequent switch bounce will not r) affect the state of the flipflop. When S3 is changed over the 1 Hz drive is disconnected from IC6 so the clock i stops. The position of S3 during time- setting with S2 is unimportant. Power Supply The clock requires a supply of about 1 A at 5 V. As transient interference on the mains supply could interfere with the timekeeping of the clock a stable, well-filtered mains supply is essential. The circuit of figure 3 is recommended, as this can deliver up to 2 A and is well stabilised. The 50 Hz drive for the clock can be derived from either side of the transformer secondary winding. Construction The p.c. board and layout for the clock are given in figure 4, and the assembly requires little comment. The BCD out- puts of the counters are brought out to the edge of the board. Display decoding is not provided on the board. Suitable decoder and display boards are the ‘Universal Display’ (Elektor No 2, Page 223). If zero suppression on the tens of hours display is required pin 5 of the 7447 should be grounded. The layout and p.c. board of the power supply are given in figure 5. The output * voltage of the supply should be set to 5 V before connecting to the clock. Parts list Resistors: R1.R2 = 3k9 R3 = 6k8 R4 = 470 SI R5 = 100 SI R6= 180 SI R7 = 1 k R8.R9.R10 = 1.5 fi PI = 1 k, preset Capacitors: C1.C2 “ 100 n C3.C4 = 1 n C5 = 2200 /i/1 6 V C6 = 220 Ai/4 V C7 = 10 p/1 6 V C8 = 470 p/6.3 V Semiconductors: B1 - Bridge rectifier, eg. B20C2200 D1 = omitted D2,D3 = DUS D4 = zener 4.7 V, 400 mW T1 = TUP T2.T3.T5 = TUN T4 = BD240 or equ. Sundries: FI = 2 A delay-action fuse Trl = transformer, 8 V/2 A Table 1. BCD code. Table 2. Truth table for IC1 (7473 connected as 1:3 divider). Figure 3. Circuit of 5-V stabilised power sup- ply. Figure 4. Printed circuit and component lay- out of the dock. Figure 5. Printed circuit and component lay- out of the 5-V stabilised power supply. 922 — elektor September 1975 G. Knapienski and F. Mitschke Phasing occurs when a portion of a signal is delayed and then mixed with the original signal. In the middle of the audio spectrum delays of less than about 100 /is will produce no noticeable effect, whilst delays greater than about 30 ms will produce a distinct echo. A delay between these limits will give the required ‘phasing’ effect. Of course, a fixed delay time will not have the same effect on signals of all frequencies. If, for example, a 1 kHz signal is delayed by exactly 1 ms and mixed at equal amplitude with the original, then the result will be a signal with twice the amplitude of the original, since the delayed signal has in fact been phase-shifted by 360°. For a 500 Hz signal, however, the situation is quite different. Here a 1 ms delay corresponds to a 180° phase shift, so if the delayed signal is mixed with the original signal the two will cancel, resulting in no sig- nal. This cancellation will occur for all frequencies for which the delay time is an odd number of half-periods. For example with a delay time of 1 ms and a 1.5 kHz signal, the delayed signal is phase shifted by 540°, or 3 half cycles. At 2.5 kHz the delayed signal is phase shifted by 5 half-cycles. As with the 1 kHz signal, all signals for which the delay time is an even number of half periods have their amplitude doubled. This is true for 2 kHz, 3 kHz, 4 kHz etc. The result is a series of peaks and nulls throughout the spectrum, as shown in figure 1. A circuit that pro- duces this type of response is known as a ‘comb filter’, because of the unusual shape of the response curve. Practical Realisation Early attempts at phasing often used tape recorders running slightly out of synchronism, but this entails a number of difficulties, not least of which being that the sound is not ‘live’, and conse- quently the musician cannot adjust the sound during the performance. There are numerous methods of achiev- ing ‘live’ phasing. Electrical delay lines are impractical for the relatively long delay times required . Electromechanical delay lines can be used to give the required delay, but their delay times are fixed by their mechanical dimensions. All-pass LC or RC phase-shift networks may also be used, but these have the disadvantage that the phase shift cannot easily be varied over a wide range. An obvious solution would be to use an analogue shift register such as the TCA590, but these devices are rather expensive. A cheap alternative is the path filter, the principle of which is shown in figure 2. SI— S7 are closed and opened success- ively at a high rate, i.e. SI is closed, then S2 is closed while SI is opened, then S3 is closed while S2 is opened and so on. This cycle is repeated continu- ously. When a particular switch is closed, the associated capacitor can charge from the input voltage through the input resistor R. The voltage on each capaci- tor is dependent on the time con- stant RC (which is fixed if all the capaci- tors have the same value) the time for which each switch remains closed (which is also fixed) and the instantaneous level of the input signal. It is therefore apparent that after a cycle of the switch sequence the voltages on the capacitors are a sample replica of the input waveform during that period (albeit slightly distorted due to the non- linear charging of the capacitors). | If successive cycles of the input wave- form and the switching cycle occur in the same phase relationship, then the voltage on each capacitor will eventually become equal to the input voltage at a particular point along the waveform. No further charging of the capacitors will occur, and the input signal will be avail- able at the output. This is true for the frequency at which one cycle of the input frequency is equal to the switching cycle time, and also for multiples of that frequency. At other frequencies the signal is heavily attenuated. Consider what happens , when a half-cycle of the input waveform is equal to the switch cycle time. Im- agine that on the positive half-cycle the peak of the input waveform is stored on « C4 in figure 2. During the negative half- cycle S4 will be closed at the trough of the waveform. The net voltage on C4 will be zero. This is true for the other 1 capacitors, so the output signal is zero. This will also occur at all frequencies elektor September 1975 — 923 where an odd number of half-cycles is equal to the switch cycle time. In practice, of course, the switching is accomplished electronically, for example by a ring counter. The result is a comb filter whose rejection fre- quencies can be varied by varying the clock frequency of the ring counter. The Q-factor can be altered by the single input resistor, R. Distortion of the output signal may be reduced by in- creasing the number of ‘paths’, i.e. the number of capacitors. A practical realisation of a 40-path filter is shown in figure 3. A 7490 decade counter and a 7474 dual D-flip-flop form a divide-by-40 counter. The out- puts of the 7474 are decoded by ten 7401 packages, each of which switches y four capacitors, making 40 in all. The outputs of the 7490 are decoded by a 74141 BCD-to-decimal decoder/driver U and used to switch the supplies to the 740 l’s via PNP transistors. The capaci- tors are thus arranged in a 4 x 10 matrix, and are switched as follows : At the start of a cycle the outputs of the 7474 are all ‘0’ so the capacitors connected to pin 4 of each 7401 are switched in sequence as the 7490 counts from 0 to 9 and the supplies to each 7401 package are switched in turn. When the count reaches 1 0 output E of the 7474 becomes ‘1’. The capacitors connected to pin 13 of the 740 l’s are switched as the 7490 , counts the second decade, and so on. The Q-control is provided by the 50 k potentiometer. The signal source must have a low output impedance and the output of the filter must be connected to a high impedance load. Applications This filter has a very narrow bandwidth, with the Q-control at maximum typi- cally less than a semitone. Various effects can be obtained with the circuit. If a narrow pulse waveform is fed in, chimes or percussion effects can be produced at the output, depending on the control * frequency. Aircraft noises and other engine noises can also be simulated by filtering out harmonics of complex tones. *” The phasing effect occurs when a clock frequency is used which is higher than the upper limit of the audio spectrum (say 20 to 100 kHz). The (^control must be set in a fairly high position. The path filter may also be used with an electronic organ or synthesizer, to produce strange effects. A particularly unusual sound can be obtained by feeding the clock input of the filter from the signal outputs of an electronic organ (squarewave outputs from div- iders, before filtering) and by feeding a noise signal into the signal input. The results are, to say the least, unlike any organ in existence. The circuit as described does have its limitations. It will not operate effec- tively below the frequency whose half- cycle is the same length as the counter cycle. Lowering the clock frequency to compensate for this introduces problems with noise due to the clock frequency and the switching of the supplies to the 740 l’s. This is aggravated by differences in the characteristics of the 740 l’s and of the transistors. Increasing the number of stages so that a higher clock fre- quency may be used will overcome many of these problems. H Figure 1. Frequency response of a comb filter. Frequencies phase-shifted by odd multiples of 180° are almost completely rejected. Figure 2. Principle of a path filter. All capaci- tors have the same value and the number of capacitors may be optionally increased almost indefinitely. Figure 3. Circuit for a practical path filter. The 7401 and the associated supply switching transistor are duplicated 10 times. Each 7401 is connected to the outputs of the 7474 as shown. Figure 4. Showing the internal circuitry of one gate in a 7401 package, and how each capacitor is connected. Various kinds of psychedelic flashing light display can be generated easily using logic shift registers. Several cir- cuits are discussed here of varying complexity. The shift register chosen for this appli- cation is the 7495. This is a four-bit par- allel/serial load, parallel/serial out, shift- left, shift right register, and was chosen because of its versatility. The circuit for generating a type of dis- play commonly used is given in figure 1 . Four lamps light in sequence until all are lit, then all are extinguished simulta- neously. The circuit operates as follows: The outputs A to D of the shift register are initially at *0’ so the mode control input (pin 6) is low. In this mode serial data is entered at pin 1 and is shifted one place right on each clock pulse. Since the serial input is held high by the 1 k resistor, outputs A to D successively go high until all are high. When output D goes high the mode control goes high with it and the shift register is now in the parallel load, shift left mode. The parallel inputs A to D are grounded so that ‘0’s are entered and subsequently appear on the outputs. The cycle then repeats. A truth table for the sequence is given in Table 1 . Figure 2 is a variation on the circuit of figure 1. Instead of changing the mode when all the outputs have become ‘1* the D output is connected to the serial input via an inverter. When the D out- put goes high this input is held low so that ‘0’s are entered. The outputs A to D go low in turn. When all are low the serial input goes high and the sequence repeats. The visual effect is that lamp A lights, then lamp B and so on until all are lit. The lamps then extinguish starting with lamp A until all are ex- tinguished. Table 2 is the truth table for this se- quence. A reset button is provided to clear the register of unwanted states that may occur at switch-on. It is also possible to operate the shift register in the serial in, shift left mode. To do this it is necessary to connect disco lights elektor September 1975 — 925 Figures 1-5. These five basic circuits show the versatility of the 7495. Each circuit gives a different output sequence. Tables 1-5. These tables show the output sequences of the corresponding circuits Figure 6. One way of isolating the control circuitry from the triac is to use trans- formers. The input to this circuit is in- compatible. 1 each output to the preceding input (D to C, C to B, B to A). Serial data is then entered at the D input and is shifted left on each clock pulse. This may be used to make a display where the lamps light in the order A to D, then extinguish in the order D to A, as in figure 3. This circuit operates as follows: the flip-flop Nl, N2 is in- itially set so that the serial input is high and the mode control is low. ‘l’s are thus entered at the serial input and appear successively at the outputs A to D. When output D becomes high T1 is turned on and the flip-flop is reset. The mode control input becomes ‘1’, reversing the shift direction. Since the D input is grounded the data entered is ‘O’, so the outputs go low starting with the D output. When all the outputs are low the flip-flop is set and the sequence repeats. The truth table is given in table 3. The circuits so far discussed are similar in that after four clock pulses all lamps are lit. It is, however a simple matter to devise a circuit where the lamps light in ^ sequence but only one at a time, by cir- culating a single T through the shift register. In the circuit of figure 4 the lamps light A in the sequence A to D, with only one lamp at a time being lit. When lamp D extinguishes lamp A lights and the se- quence repeats (table 4). The circuit op- erates as follows: on switching on the A to D outputs will set randomly so that more than one output may be high. This would mean that a number of ‘l’s would be circulating, whereas only a single ‘P is required. For this reason a reset button is provided. When SI is de- pressed the flip-flop comprising N5 and N6 is set, taking the serial input high. At the same time the mode control is taken high by the other half of SI, so that on the next clock pulse the register shifts the ‘0’s from the grounded A to D inputs to the corresponding outputs, clearing the register. When the switch is released the register is in the serial-in, shift right mode, so on the next clock pulse the ‘P present on the serial input will appear at output A. The output of N2 will go low, resetting the flip-flop N5, N6 so that the serial in- put is low. On each successive clock pulse the ‘P on the A output is shifted one place to the right until it appears at output D. When this occurs the output of N 1 goes low, setting the flip-flop. A ‘P now appears at the serial input, and the process repeats. Figure 5 shows a variation on this cir- cuit, in which a ‘P travels back and forth from one end of the register to the other (table 5). The circuit is initially reset by pressing S 1 . This sets the flip- flop Nl, N2 so that a ‘P appears at the serial input. It also puts the register in the shift-left mode, so that the ‘0’ on the grounded D input is shifted left, clearing the register. The flip-flop com- 926 — elektor September 1975 disco lights -©5V prising N3, N4 is reset, so that the out- put of N3 is low. On releasing S 1 the register mode con- trol is connected to the (low) output of N3, so the register is in the shift-right mode. On the first clock pulse the ‘1’ applied to the serial input appears at the A output. It is inverted and resets the flip-flop Nl, N2 so that no more *l’s are entered. The ‘1’ which is in the regis- ter is shifted right on each successive clock pulse until it reaches the D out- put. Flip-flop N3, N4 is then set, revers- ing the shift direction. When the ‘1’ again reaches the A output flip-flop N3, N4 is reset and the shift direction again reverses, and so on. The number of variations on these cir- cuits is, of course, limited only by the ingenuity of the constructor. Actual switching of the lamps is ac- complished using triacs. Unless the entire circuitry is housed in an insulated box the logic circuitry must be isolated from the mains. This may be ac- complished by either transformer or op- tical isolation of the control circuitry from the triac, and suitable circuits are given in figures 6 and 7. In figure 6 the secondary voltage of Trl is full-wave rectified and applied to the collector of the transistor via the primary of Tr2. When the transistor is turned on by one of the outputs of the Figure 7. A more elegant solution is to use opto-isolation. Figure 8. Two NANO gates (or inverters) can be connected as an astable multivibrator. This provides a simple clock generator circuit to drive the 7495. Figure 9. If four outputs are considered in- sufficient, circuits 1, 2 and 4 can be extended ad infinitum in this way. Figure 10. Circuits 3 and 5 can also be readily extended to give any number of additional outputs. register, current flows through the primary of Tr2 and the current induced in the secondary triggers the triac. The choice of transformers is not critical. Trl can be a small bell transformer, whilst Tr2 should have a ratio of about 1 : 6 and can be a miniature type since only a small current flows through it. Of course Trl and the bridge rectifier are required only once in the circuit, but the transistor. Tr2 and the triac must be repeated for every output from the shift register. With this circuit trig- gering of the triac is not optimum. Phasing of the transformers is import- ant, so if the circuit does not work first time reverse the polarity of one of the windings. A more elegant solution is to use opto-l isolation, as in the circuit of figure 7.1 This is simply a conventional triac dim-1 mer with the main potentiometer! replaced by a light-dependent resistorl housed in a light-tight enclosure with a| LED. When the transistor is turned on by an output of the shift register the LED lights and the illumination causes the resistance of the LDR to fall. The triggering point of the triac is thus ad- vanced and the lamp lights. The base current of the transistor in both these circuits is about 3 mA, so they can easily be driven by the outputs of the shift register. The choice of diac and triac for both these switches de- pends on the maximum load to be switched. A simple clock generator circuit is given in figure 8. This is simply two NAND- gates or inverters connected as an astable multivibrator. A variable fre- quency pulse generator could also be used so that the travelling speed of the light pattern could be altered. Figures 9 and 10 show how the discolights may be extended with several shift registers. Figure 9 is intended for extension of figures 1, 2, and 4, and figure 10 for the extension of figures 3 and 5 . H elektor September 1975 - 927 rt^e *° r As the gain in an OTA can be controlled by the current from an external source (the bias current IaBC). possibilities are opened up for new applications which have up to now been difficult to perform satisfactorily with discrete components. A simple application of the OTA, for example, is amplitude modulation. Al- though it is basically possible to effect this with one or more discrete transis- tors, closer inspection shows that dis- crete circuits do not achieve all forms of amplitude modulation really satisfac- torily. Tremolo (amplitude modulation of a signal which is to be reproduced acoustically) is not easy to achieve electronically without relatively high distortion or interference. Other appli- cations of the OTA such as multiplexing or sampling of signals are more success- ful than with other methods because of the OTA’s high slew rate of 50 V//jsec. Automatic volume control is also an obviously attractive application for OTAs. More applications of two types of OTA, the CA 3080 and the CA 3094 AT, will be given in future issues. These are the most interesting of the large range of OTAs which have been developed by RCA. The CA 3094 AT has in fact been developed from the CA 3080, and the only basic difference concerns the output circuit. Linear transconductance (forward slope) Before using the OTA in practical cir- cuits, it is important to understand the meaning of the term ‘forward slope’ for which the abbreviation ‘g m ’ is used. The term g m is expressed in mho (1/ft) or millimho ( ^ x j Q3 )• The amplification factor of a normal operational amplifier (known as a voltage amplifier) corre- sponds to the g m of a voltage-driven current source (i.e. an OTA). The relationship between the output current and the corresponding input voltage of an OTA is: Alout = gm x AVjn. The output signal of an OTA is thus a current which is proportional to its g m . The output voltage (AV OU {) appearing as a result of the output current, Al ou t, in an OTA is the product of this current and the load resistor. CA 3080 Figure 1 shows a simplified circuit of the CA 3080. Tj and T 2 in figure 1 form a differential amplifier, which is also found in most normal operational amplifiers. W, X, Y and Z are known as current mirrors. A current mirror consists in principle of two transistors, one of which is connected as a diode. Figure 2 gives the circuit of a current mirror of this type. As the transistors T a and Tb are supposedly identical, a current I" into T a results in a second current I into Tb with the following relationship to I' : I _ «’ I' a' + 2 In this formula a' is the current amplifi- cation of transistors T a and Tb- A current mirror can be regarded in prac- tice as a current source in which the out- put current (I) is almost identical to the control current (I'), and in which the two currents I and I' can in fact be regarded as isolated from one another. A disadvantage of the current mirror as shown in figure 2 is that it is sensitive to small differences in the current ampli- fications of transistors T a and Tb, these differences resulting in the currents I' and I not being precisely equal. This effect can be greatly reduced by the inclusion of a third transistor (Ti in figure 3). Current mirror W in figure 1 has the circuit shown in figure 2, while current Transistors T 1 and T 2 form the differential input amplifier. W, X, Y and Z are so-called current mirrors. Figure 2. A current mirror can be simply made up with two transistors (T a and Tb). The drive current I ' gives rise to a current I which is proportional to I'. Figure 3. The current mirror of figure 2 is sensitive to differences between the current gains of the two transistors (T a and Tb). Addition of T] reduces this sensitivity con- siderably. ota | mirrors X, Y and Z are as shown in figure 3. It should also be noted that Y and Z have PNP transistors. The complete circuit diagram of the CA 3080 is given in figure 4. The circled points indicate the connection numbers in the TO-5 housing. This housing, as seen from the upper side, is shown diagrammatically in figure 5. In one of the RCA data sheets a drawing corresponding to figure 5 shows the reference tip between connections 1 and 8. This can lead to confusion: the drawing in figure 5 is correct. In the circuit shown in figure 4, T i and T2 are the differential input amplifier. Transistor T3 is the common emitter impedance of this differential amplifier. The most significant difference from the input stage of a normal opamp is that T3 is part of a current mirror, so that its collector current is equal to the bias current (IABC)- The value of the collector current of T3 determines the emitter current of the differential amplifier T1/T2, and this provides an effective means of controlling the overall transconductance. The g m of an OTA in normal ambient temperatures ( 1 6°C . . . 27°C) is given by : 8m = 19.2 x I abc I in which g m is expressed in millimhos ( 1/J2 x 1(T 3 ) and IaBC ' n mA. In figure 4 the output signal of the OTA is taken from the collectors of T9 and Tjo (connection 6) which form part of the current mirrors Z and X respectively in figure 1. As IaBC ‘ s varied, the g m of the OTA changes and therefore the output current does likewise; hence: Alout = g m x AVj n = 19.2 x IaBC x ^in (at normal temperatures!) The OTA can easily be made to operate as a voltage amplifier by connecting a load resistor Rl between the output and circuit earth. The output voltage then becomes: AVout = RL x 19.2 x I ABC x AV in in which IaBC > s > n mA > Rl I s In kft, V ou t and Vin are in volts. Characteristics of the CA 3080 Table 1 gives various important limiting values for the CA 3080 and the CA 3080 A. The difference between these two types is related only to their working temperature ranges. In addition to these characteristics, which are for the specified supply voltages and an I ABC of 500 11 A, it can be said that the limit of the working frequency range is about 2 MHz. The quoted input Figure 4. Complete circuit of the CA 3080 1C. The circled numbers correspond to the coding of the connecting leads. Figure 5. Connections for the CA 3080 1C are the same as on the flA 709 except for Pins 1 and 5. The drawing shows the top view of the 1C. Figure 6. These curves show changes in out- put current (Aloutl plotted as functions of changes in the input voltage (AV; n ). Figure 7. Input resistance (Rj n ) as a function of the so-called bias current OaBC)- Figure 8. As with the input resistance, the output resistance of the CA 3080 is depen- dent on the bias current Iabq. As figure 7 and this graph show, both relationships are completely linear. Figure 9. The CA 3080 connected as a D.C.- coupled differential amplifier. Gain can be varied by potmeter Pj from about 30 to about 100 times. Table 1. Characteristics and maximum rating of the CA 3080 and CA 3080 A ICs. Maximum ratings: Characteristics: DC supply voltage (V b = +15 V; — V b = -15 V between +V b and lABC = 500MA) "V b : Input capacitance: 3.6 pF Differential input Input resistance: 26 k£2 voltage: Common mode input Input bias current: 2 pA voltage: +V b to - V b Slew rate with unity gain: 50 V//JS Input signal current: Bias current (IabC> : Output short-circuit Peak output current: 500 flA duration: no limitation Peak output voltage : Device dissipation: positive Operating temperature negative -14.4 V Amplifier supply current: 1 mA CA 3080 Device dissipation: 30 mW CA 3080 A -55“ to + 1 25“C resistance of 26 k is dependent on the value of I ABC- If a value of 1 MS2 is chosen for the output load resistor, the voltage gain is easy to work out from the character- istics given in table 1 : It can be deduced from this last formula that the voltage gain can also be varied by changing the load resistance. The curves in figure 6 show that the overall characteristic of the CA 3080 is completely linear for small inputs to the differential amplifier. The curves show the relative values of AI ou t and the deviations from linearity as functions of the relative values of AVj n . Figure 7 shows the input impedance of the CA 3080 as a function of the bias current I ABC- The maximum impedance attainable in this OTA is about 40 Mf2 with a bias current of 0. 1 /rA. The output impedance is also, of course, (j dependent on the value of IaBC- ( Figure 8 shows that this relationship is ! linear. 1 For the sake of completeness, it should be said that the characteristic of figure 7 also holds good for the CA 3094 AT. Figure 8 also holds good for the CA 3094 AT, but only for its current output. This IC has other outputs. OTA - opamp Figure 9 shows a practical circuit for the CA 3080 from which a comparison can be made with normal opamps. The power supply is symmetrical at ± 6 V. Both inputs are D.C.-coupled and are connected to chassis earth through Ri and R 2 respectively. Resistor R 3 of figure 9 is introduced in order to obtain voltage amplification, as in an opamp. The usual feedback from the output to the inverting input of the IC is miss- ing, because the gain can be controlled by the bias current IaBC at Pin 5. I ABC is eas y to calculate. While re- calling that the emitter of T 3 is connec- ted to — Vb (pin 4), assume that IaBC is drawn via a resistor R x from chassis earth, which is 6 V positive in relation to — Vb- The relationship then becomes: •ABC Vb ~ 0,7 Rx In this formula, I A BC is in mA, while v b is in volts and R x is in kfi. The quantity 0.7 is the base-emitter poten- tial of T 3 in figure 4. To find the value of R x for a desired value of IabC- the formula can, of course, be rewritten: R^V 07 . *ABC In figure 9 R x is replaced by the combi- nation R4, R s and Pj. When the slider of Pj is at the positive end of its travel (i.e. at 0 V), the voltage across the series connection of R x and the base- emitter junction of T 3 is Vb, so that •ABC = — Z °' 7 * 0.53 mA. K4 It therefore follows that the voltage gain is: A=R 3Xg m xI ABC* 5 ! Ox 1 9.2x0.53 s * 1 00. When, however, the slider of Pj is at the negative end of its travel (the junction of R s and Pi), the voltage relative to -Vb at the slider of Pi is: R4//P1 x (V b + 0.7 I? ) v x — - R4/P1 + Rs The effective voltage across R 4 is there- fore: 2.2 V-0.7 V= 1.5 V so the bias current is given by: •ABC ** mA = 0. 1 5 mA. The voltage gain is therefore: A*»R 3 xg m xI ABC 5 * 5 ! Ox 1 9.2x0. 1 5=29X If the gain of this IC is allowed to drop substantially, considerable distortion may result unless special attention is given to the design of the differential inputs. Should the input transistors Ti and T 2 (figure 4) not be exactly matched, their emitter currents will differ when IabC is low, an d this will cause distortion. In this connection, the following rules of thumb apply: a. If the OTA gain is fixed, resistors Ri and R 2 (figure 9) must have values which are lower, by a factor of at least 2:1, than the value of input impedance read from figure 7 for the relevant value of IaBC- b. R x and R 2 must have the same value when I ABC is less than about 0.5 /i A. c. For fixed gain with values of IabC between 1 pA and 10/iA, the values of resistors Rj and R 2 may differ by a factor of 2. d. When IaBC is over 10 /xA, R, and R 2 may differ in value by a factor of 4. e. If the gain is to be variable over a range greater than 1 : 5, resistors R t and R 2 must have values lov/er, by a factor of at least 2, than the 930 — elektor September 1975 value of input impedance, indicated by figure 7, for the maximum I ABC- Negative feedback Negative voltage feedback can be used with an OTA as it can with a normal opamp. Figure 10 gives an example of a circuit for a CA 3080. The bias current I ABC is determined by R4- The poten- tial across this resistor is the negative power supply (15 V), less the 0.7 V base-emitter voltage which was discussed in relation to T3 of figure 4. In this case the value of bias current is given by: _ 15-0.7 . UK - — ^ '« M so that g m works out at 19.2 x I ABC = 2.74 mmho. The voltage gain given by a CA 3080 in the circuit shown in figure 10 is not determined solely by the value of the load resistor R5 , but also by Rj and R 3 . In the first place, the effective output load resistance is Rs and (R3 + Ri) in parallel. In the second place, the voltage developed at pin 6 across this effective output load is fed back to the inverting input (pin 2) with a step-down ratio R,/(R,+R 3 ). The effective voltage gain between the input and pin 6 is thus: Af = 1 +(A 0 -f) 8nr R L 1 +(gm* R L-0 8m • [( R i + r 3 )^ r 5 ] l+g m [(R, +R 3 WRs]. *= gm * Rs — - = lOx 1 + 8m * R s • (f is the feedback factor .) It can be seen from figure 10 that if R 3 is omitted there will be no voltage fed- back from the output. This is equivalent to making R 3 infinitely large in the foregoing calculations, and results in in the voltage gain being increased by a factor of about 8. Table 2. Characteristics and ratings of the CA 3094 AT. Maximum ratings: DC supply voltage be- maximum tween +V b and — V b : Differential input 36 V Common mode input ±5 V voltage: +V b to-V b Input signal current: 1 mA Bias current ( • ABC) Output current: 2 mA peak: 300 mA average: Device dissipation : 100 mA without heat sink: 630 mW with heat sink: 1.6 W Peak dissipation (1 mS): Operating temperature 10W range: —55 Characteristics: (+V b = 15 V; -V b = -15 V; ■abc = 100 AIA). 0 +125°C Differential input capacitance: Differential input resistance: 2.6 pF •'ABC = 20 ^iA): 1 Mfi Input offset current: Input bias current: 0.2 f/A Device dissipation: Bandwidth (Unity gain): 30 MHz Amplifier bias voltage: 0.68 V If a comparison is now made between the circuit of figure 10 and a normal opamp, such as the /iA 741, a number of similarities become evident. Both the OTA and the opamp can be operated as voltage amplifiers, and voltage nega- tive feedback can be used with either. Both can have either symmetrical or asymmetrical inputs, inverting or non- inverting. The OTA, however, becomes a pure current source when it has no load resistance; a feature which can be advantageous for some applications. Besides this, the OTA has the feature that, as the transconductance is varied by varying the bias current, the input and output impedances also vary over elektor September 1975 - 931 ota Figure 10. This circuit incorporates negative feedback from the output through R3 to the inverting input. Figure 11. A CA 3080 connected as an A.C.- coupled asymmetrical amplifier. Negative feedback is taken from the emitter of T 1 through R3 to the inverting input of the 1C. Figure 12. Detailed circuit of the output section of a CA 3994 AT OTA. The difference from the CA 3080 consists of the addition of resistors R1/R2 and transistors T yJJ 13. Figure 13. Functional diagram of the CA 3094 AT. The corresponding output of the CA 3080 (Pin 6) is connected in this case to Pin 1. a wide range. If it is important for a particular application that one of these parameters (but not the other two) should have a specific value, it can be adjusted to this value by controlling the bias current. Yet another feature possessed only by the OTA is that the gain can be con- trolled as may be required by D.C. or A.C. potentials, thus making amplitude modulation, sampling or switching functions possible. Output buffer stage Table 1 shows that the peak output current of the CA 3080 is only 500 //A, and this can be a drawback in a number of applications; moreover a ‘power’ OTA such as the CA 3094 AT costs twice as much. A simple solution is given in figure 1 1, which shows a buffer transistor follow- ing the OTA. By this means the output current (AI ou t) of the OTA is multiplied in the same ratio as the current amplifi- cation of Ti . Another advantage accru- ing to the addition of Tj is that, being an emitter follower, its output im- pedance is low. The load impedance which the OTA ‘sees’ at its output is equal to the values of R s , R 6 and the input impedance of Ti , all in parallel. The fact that the CA 3094 AT has been developed shows that RCA themselves have, indeed, given thought to the need for higher output currents. This OTA is equivalent to the CA 3080 except for the addition of two resistors and two transistors. Figure 12 shows in detail the output circuit of a CA 3094 AT. A comparison with figure 4 shows that R1/R2 and Ti/T 2 have been added in figure 12. Some of the characteristics of the CA 3094 AT are given in table 2, and the connections are given in figure 13. Pins 8 and 6 become power output points for ‘sink’ or ‘drive’ cur- rents respectively. The low-power out- put, which is at Pin 6 in the CA 3080, is brought out at Pin 1 in the CA 3094 AT. H The store of dried feed is held in a trough with V-shaped sides (figure 1). At the bottom of the trough is a cylin- drical container which runs the length of the trough, and which has one side cut away. This cylinder is driven, via a reduction gear, from a small model motor. As the container rotates it will fill when the open side is uppermost, and empty into the aquarium as it ro- tates. The number of revolutions made at each feeding session, and hence the amount of food delivered, is controlled by the electronic circuitry. A cowl at the bottom of the dispenser prevents splashing caused by the fish or the aer- ator from making the feed sticky and thus clogging the dispenser. The circuit In figure 2, TI is an emitter-follower whose base potential is controlled by a light dependent resistor R1 and a potentiometer PI. This is followed by a Schmitt trigger, T2 and T3, which has a large degree of hysteresis. This drives T4 via R9 and zener diode D2. During dark- ness the resistance of the LDR is high. The emitter potential of TI is therefore high, T2 is turned on and T3 is turned off. Hence T4 is also turned on. When daybreak comes the resistance of the LDR drops, the emitter potential of TI drops, and when the switch off threshold of the Schmitt trigger is reached T2 turns off and T3 turns on. 1 T4 therefore turns off. Point A goes up to supply potential. The switch-on threshold at daybreak can be adjusted with PI . The hysteresis of the Schmitt trigger is so great that even large brightness variations during ' the day will not cause spurious trig- gering. However, care must be taken to ensure that the LDR is screened from room lighting so that spurious trig- gering does not occur in the evening. The motor control circuit is shown in figure 3. When T4 switches off at day- break, T5 turns on. This shorts out the base of T6 through C2, and T6 turns off until C2 has charged sufficiently through R15 and P2 for T6 to turn on again. During this time T7 and T8 are turned on and the motor runs. The charging rate of C2, and hence the motor running time, can be adjusted by P2. In the evening when T4 turns on, T5 turns off but this does not affect the ■ state of the following stage, so no feeding occurs. If the fish feeder is to be used other than at holiday times the triac switch of figure 4 may be used to control the aquarium lighting. It is important to in- clude C3 across the choke of the fluor- escent tube to avoid high voltages being applied to the triac. If the lighting cir- I cuit is connected to the automatic feeder it is imperative to ensure that the finished construction is adequately in- sulated as the ground connection of the < fish feeder is connected to the mains neutral. No part of the circuit should be accessible, and in particular the motor j should be insulated, including the drive shaft. Potentiometer P2 should have a plastic shaft, and the whole assembly should be mounted in a plastic box, with no metal protrusions. ri -stable elektor September 1975 - 933 It is possible to use two NAND or NOR gates to make up a flipflop - a circuit with two stable con- ditions. The process can be extended to obtain circuits with three or even more stable states. The arrangements shown in figure 1 both have 3 stable states. The state taken up by the outputs will depend on the input conditions applied. These cir- cuits have the objection that correct operation is only guaranteed when drive is applied to two of the inputs at once (see table 1). It is however possible to modify the cir- cuits so that a single input drive will produce the desired output state. The circuit as a whole becomes more exten- sive; but it becomes easier to use. Figure 2 shows the modified arrange- ment. The operation of this circuit can be followed from table 2. Figure 3 shows a master-slave shift regis- ter. If C is at logic V, then the OR-gate outputs will also be ‘1’, so that the state of Q1-Q2-Q3 does not change. If C becomes ‘O’, the AND-gate outputs will also be ‘O’, so that the state of Q4-Q5-Q6 is held. Suppose for example that C is logic “O’, with Ij = ‘O’, I2 = ‘0’ and I3 = ‘1’. We find that Qi = ‘1’, Q2 = ‘1’ and Q3 = ‘O’. Since C is ‘0’ the state of Q4-QS-Q6 is maintained. If C now goes to ‘1’, the outputs Qi, Q2 and Q3 will not change. This state is also the state at the inputs I4, Is and 16. Q4 therefore becomes ‘O’, Qs also ‘0’ and Q6 ‘1’. This shows that the input information ‘0’-‘0’-‘l ’ appears, after one clock pulse, at the output. H 3 934 - elektor September 1975 roll out the bandit L. Wiechers This oscillator was designed for driving electronic games of chance, such as the 'three-eyed bandit' (Elektor No. 2 page 238) or an electronic 'roulette wheel'. The disadvantage of the 'three- eyed bandit' is that a stop button must be pressed to stop the three oscillators and obtain the final display. Thus the tension and : anticipation obtained with a real one-armed bandit as the number drums slowly grind to a halt is | missing. The voltage-controlled oscillator overcomes this by pro- | viding an output whose frequency ' slowly reduces until it finally , stops. This can also be used to [ simulate the 'rolling out' of the ball in a roulette wheel. r The circuit is based on the well-known & astable multivibrator (figure 1 ). The fre- | quency of oscillation of this circuit is L determined by the charging current into 1 Cl and C2 through Rb 2 and RBI when U either of the transistors is in the cutoff R state. The multivibrator can be turned into a simple VCO by connecting Rg j ■ and Rj}2 to a seperate supply instead of to +Vb. Increasing the voltage applied to the base resistors will increase the " charging current through them into Cl and C2, and will hence increase the fre- quency of oscillation. Reducing the voltage has the opposite effect. There are however, certain limitations to this simple approach. The base res- sistors perform two functions. When (for example) T1 is turned on Rui sup- plies its base current. The minimum cur- rent must be such that the transistor remains in saturation. This places a restriction on the minimum voltage that may be applied for a given base resistor. When T 1 is turned off and T2 is turned on, Rgl supplies the discharge current for C2 whilst R1 supplies the charging current for Cl. For correct operation Cl must have charged up to almost +Vb before T1 turns on again. This means that C2 must discharge more slowly than Cl charges, and this limits the maximum control voltage that may be applied to the base resistors. In practice frequency changes of between 10 : 1 and 50 : 1 can be achieved, depending on the gain of the transistors. This is in- sufficient for tills application. Base current feed through zener diodes The limited frequency range can be ex- tended by the circuit of figure 2. Nor- mally the coupling capacitors supply a portion of the base current whilst they are charging from the collector resistors, but this ceases as soon as the capacitors are charged. The zener diodes perform two functions: 1. they limit the voltage to which the coupling capacitors charge, and hence the time required for charging. 2. they provide a D.C. path for the transistor base current, even when the capacitors have charged. This means that the base resistors only provide the discharge current for the capacitors with the transistors in a cutoff condition. They can thus be much larger. Also, since one transistor is always cut off, only one base resistor is required (shown dotted in figure 2) provided the transistor bases are isolated by diodes. When this circuit is used as a VCO by connecting Rb to a control voltage a elektor September 1975 — 935 Figure 1. A basic astable multivibrator. This may be voltage-controlled by connecting the base resistors to a variable voltage instead of + v b . Figure 2. Addition of zener diodes makes transistor base current almost independent of base resistors. The two base resistors can be replaced by a single resistor and two Figure 3. Base resistor replaced by a voltage- controlled currant source. Figure 4. Addition of emitter followers im- proves risetime without sacrificing loop gain. T6 further improves risetime and drives TTL. frequency range of between 200 : 1 and 500 : 1 is obtainable. Decaying frequency characteristic The next step is to achieve the gradual decay of frequency required. This is accomplished in the circuit of figure 3. When the pushbutton is pressed C3 is charged rapidly. The voltage on C3 turns on T3 which causes the oscil- lator to start. As C3 slowly discharges the collector current of T3 decreases and the oscillator frequency reduces until the voltage across C3 is less than about 0.6 V, when T3 cuts off and the oscillator stops. The final circuit Figure 4 shows the final circuit. Emitter followers T4 and T5 are incorporated to provide a low impedance charging path for the coupling capacitors, thus improving the rise time of the waveform without reducing R1 and R2, which would reduce the loop gain. T6 converts the output to a level suitable for driving TTL circuits. The discharge rate of C3, and hence the ‘rolling out’ time, is adjusted by PI. The initial frequency of oscillation is ad- justed by P2. Note that Cl and C2 should be non-electrolytic types. With the component values shown the results obtained were as follows: Starting frequency 100 to 300 Hz. Final frequency about 0.3 Hz. ‘Rolling out’ time 25 s maximum. j. This simple triac dimmer can be used to control incandescent filament lamps up to 1 500 W. The circuit operates on the phase-control principle. The main con- trol is provided by P2. This determines the rate at which C2 charges and hence the point along the mains waveform at which the voltage on C2 reaches the breakdown voltage of the diac, which is when the triac is triggered. PI, in con- junction with R1 and Cl determines the minimum brightness level, or alterna- tively may be used as a fine brightness control. Interference suppression is provided by R2 and C3. Construction The printed circuit board is very com- pact and can easily be accommodated inside the modern, square type of flush- mounting switch panel, or in a small box for portable applicatiqns. The following safety points should be noted. No part of the circuit should be access- ible from the outside. The case should preferably be made of plastic or other insulating material, and fixing screws for the board should be nylon. If a metal case is used the board must be ad- equately insulated from it and the case should be earthed. The potentiometer should have a plastic spindle. M 936 — elektor September 1975 .L. Krielen has \c?* d ' 9 i 2gs%gr^ «#&£<*** **^ The dual-slope technique is one of the simplest and most reliable DVM sys- tems. The voltage to be measured is fed to an integrator for a fixed period of time. The current into the integrator, and therefore the charge on the inte- grator capacitor at the end of this period, is proportional to the input volt- age. The capacitor is then discharged at a (known) constant current and the time taken for the capacitor to com- pletely discharge is measured. Since the discharge current is constant the time taken to discharge is proportional to the original charge, which in turn is pro- portional to the input voltage. The dis- charge time is measured by feeding clock pulses from an oscillator to a digi- tal counter until the voltage on the ca- pacitor reaches zero. The same oscillator is used to determine the original charge time. This means that any long-term variations in the oscillator frequency are unimportant since they will affect both the charge time and the measured dis- charge time equally. The long-term stab- ility and absolute frequency of the oscil- lator are thus unimportant. The only reference standard in the DVM is the constant discharge current, which must be stable. Looking at the system mathematically: Current into integrator Ij = V/R, where V is voltage to be measured and R is in- Fiflure 1. Bock diagram of the complete DVM. The arrow! In the various connections indicate the direction of action. Figure 2. The input voltage applied. Figure 3. The time axis. The time ti-t2 is the charging time. t2-t3 is the discharge time, and t3-to is the display time. Figure 4. Output vottaga of the reset pulse generator. Figure 5. The input voltage to the integrator. Figure 6. The di scha rge current of the inte- grator. Figure 7. The output voltage of the integrator. Figure 8. The output voltage of the zero- crossing detector. Figure 9. The dock pulses applied to the counter. They first consist of 100 reference pulses, which determine the charging time, followed by a number of pulses proportional to the voltage of the input signal. The fre- quency of these pubes can be assumed to be constant during the time tvQ. Figure 10. The dock generator. Via line A the pulses go to the count gate, whilst via line B the reset pulse generator is driven. Figure 11. The reset putse generator. This supplies reset pubes to the counter (via C and D) , and a start pulse to the control logic (via E) . tegrator input resistor. Charge on integrator capacitor at end of charge period Ati Q-l,4t, - g - A«i : Time taken for capacitor to discharge at constant current I 2 Q__ VAt, h IjR Since At] and At 2 are derived from the same oscillator it can be seen that a vari- ation in oscillator frequency will affect both Atj and At 2 equally, and the final result will remain the same, provided I 2 does not change and R is fixed. dual slope dvm elektor September 1975 — 937 The block diagram of the DVM is given in figure 1 and an operational timing diagram in figures 2-9. The timing dia- gram is drawn for both a positive and ! a negative input voltage. 1 The sequence of operation is as follows: the input chopper applies the input volt- age (figure 2) to the integrator for a fixed time t 4 -t 2 (figure 3). The chopped input to the integrator is shown in fig- ure 5. During this time the integrator output rises linearly as the capacitor charges (figure 7). The step in the inte- grator output waveform at the beginning and end of the charge period is ex- plained in the detailed description of the integrator later in the text. At the end of the charge period the inte- [ grator is disconnected from the input voltage and is connected to the dis- charge circuit. The integrator capacitor discharges linearly during the period tj- t 3 (figure 6). During the whole period t j -t 3 the output of the zero- crossing detector (figure 8) is positive. When the voltage on the integrator ca- pacitor reaches zero the output of the zero-crossing detector falls to zero. This | is used to control the clock pulses to the counter (figure 9). The operation is ef- fected by the control logic in the block diagram. Before each measuring period the counter and control logic are reset by a pulse from the reset oscillator f (figure 4). Measurement of a negative voltage is performed in a similar manner. The only differences are that the output of the zero-crossing detector is negative. This is detected by the polarity detector and is used to reverse the polarity of the con- stant current from the discharge circuit. (Otherwise the integrator output, being already negative, would simply become more negative and would never cross l zero.) A refinement is incorporated in the form of a drift compensator circuit, which nulls out the effect of zero drift in the integrator and zero-crossing detec- tor. Circuits in the DVM Clock Generator • The clock generator, which provides drive pulses for the counter, is shown in figure 10 and consists simply of a two- transistor astable multivibrator with a frequency of approximately 15 kHz. As stated earlier, the long-term stability of this oscillator is unimportant. The Reset Pulse Generator This circuit is shown in figure 1 1 and is based on a programmable unijunction transistor, T14. The gate of this device receives a D.C. bias from R42 and R43. Pulses from the clock generator are applied to point (B) and charge up C7 through DIO and R41. When the uni- junction fires C7 discharges through the unijunction and R44, and the voltage across R44 causes T10 to turn on. This causes Til to turn off. A negative- going pulse is therefore available at the collector of T10 and a positive-going pulse is available at the collector of T1 1 . The time between reset pulses is deter- mined by the time constant R4 1 x C7, and in this case is one second. The inter- val between reset pulses determines the measurement repetition rate and also the time for which each reading is dis- played. It may be altered to suit per- sonal taste, provided it is longer than the measuring period t 3 -t 3 . C7 should be a low-leakage type, prefer- ably tantalum. The Counter The counter circuit (figure 12) consists of two 7490 decade counters and a JK flip flop (half of a 7473). The 7490’s count the two least significant decades and drive 7447 seven segment decoders and LED or Minitron displays. The JK flipflop counts the ‘hundreds’. Since the maximum display is 199 only a one need be displayed by the hundreds dis- 938 — elektor September 1975 dual slope d»m play. For economy, a seven segment dis- play is not used but simply two LED’s in series. The other half of the 7473 is used in the control logic. Clock pulses to the counter are gated by a two-input NAND-gate (quarter of a 7401). Input Chopper The input chopper (figure 13) connects the input voltage to the non-inverting input of the integrator during the charge period, 1 1 -t 2 . For the rest of the measurement cycle it grounds this input. The circuit functions as follows: during the interval t,-t 2 point H is at logic ‘1’ (+5 V) so T1 is turned off. T2 is also turned off. The gate of FI is held at about — 10 V so FI is cut off. The gate of F2 is held at about -1.2 V, so F2 is turned on. The input voltage therefore appears at point I via the FET F2, and is thus fed to the input of the integrator. At time t 2 point H becomes low, so T1 and T2 are both turned on. The gate voltage of FI becomes about -2 V, so it conducts and grounds the input of the integrator. The gate voltage of F2 be- comes about - 1 0 V, so it is cut off and the input voltage is disconnected from the integrator. The Integrator The integrator of figure 14 serves to establish a voltage-time relationship, i.e. the number of clock pulses counted must be proportional to the input volt- age. The circuit operates in the follow- ing manner: to achieve a reasonably high input im- pedance without additional buffer amplifiers a non-inverting integrator configuration is used. When the input voltage is applied to the input I by the input chopper, the output of the 741 will swing positive. Since C2 appears as a short circuit to this step input there is 100% negative feedback through C2. The output voltage of the 741 must therefore assume the same value as the voltage on the inverting input (pin 4), which by definition is the same as the input voltage on pin 5. The input volt- age thus appears at the output as a positive-going step. Since there is now a voltage across R12 a (constant) current flows through it which is proportional to the input voltage. Since no current can flow into the inverting input of the 741 this current must flow into C2. Since the current is constant the charge on the capacitor, and therefore the volt- age across it, increases linearly. The capacitor is allowed to charge for a period of 100 clock pulses. The voltage across C2 is then v _ li • At _ Vjn • At c 2 "r, 2 • C 2 where At represents the time interval 1 1 - fa- At time t 2 the input chopper discon- nects the input voltage and grounds the non-inverting input of the integrator. This causes a negative-going step, which cancels out the earlier positive-going step. The voltage on the inverting input of the amplifier is now zero, so the volt- age across C2 is the same as the output voltage. When the discharge circuit is connected to point J (the inverting input) the inte- grator begins to function in the in- verting mode. The discharge circuit sup- plies a constant current 1 2 into the ca- pacitor of opposite polarity to the charging current. The capacitor thus discharges linearly. The voltage on the inverting input is, by definition, zero, so as the voltage across C2 falls so does the Figure 12. The counter. C and D are reset in- puts, A is the count input. F the driver for the count gate. Output G supplies a pulse to the control logic at the one hundredth count pulse. Figure 13. The input chopper. It is driven via line H, and during the time t 2 -t2 it passes the input signal on to the integrator (via line ll. Figure 14. The integrator. I is the input and L the output. The lines J and K, come from the discharge circuit and the drift compensator, respectively. C2 is the integr a tion capacitor. PI serves for zero-adjustment: with input I to earth and the lines J and K interrupted, the output L must be adjusted to 0 with this potentiometer. Figure 15. The zero-crossing detector. It amplifies the output voltage of the integrator (line L), and drives the drift compensator and the polarity detector (via M and N). Figure 16. The polarity detector. This is in fact a three-position switch: for input voltages higher than +600 mV output 0 is low' and P 'high'; for voltages betvman +600 mV and -600 mV both outputs are Tiigh'; whilst for voltages below -600 mV 0 is high and P is low. Figure 17. The polarity indicator. It drives the pilot lamps, depending on the polarity of the input signal during the measuring period. Figure 18. The discharge circuit. This is switched on via line S or T from the control logic, and ensures that the integration ca- pacitor is discharged via line J. The DVM ■ calibrated with adjustment potentiometer P2 for positive, and with P3 for negative input voltages. Both are adjusted until the counter indicates one unit per millivolt. 741 output voltage (which is identical). During this time the counter is counting clock pulses, until the zero-crossing detector monitors zero volts on the output of the 741. The discharge time At x is given by: voltage on C2, I, • At _ l a « At x C 2 C 2 therefore but At x I, • At Ij It _Vjn R, 2 therefore _ Vjn * Rial Since At, R12 and I 2 are all fixed At x is proportional to Vjn. The Zero-Crossing Detector This circuit also uses an op-amp (fig- ure 15), but in this case a 709 is used which has a greater slew-rate than the 741. The circuit has a high gain, about 70 x, so a small swing of the input volt- age positive or negative will make the output swing hard over to plus or minus 10 V. D5 and D6 provide input protec- tion by limiting the voltage on pin 5 of the IC to about ±0.2 V maximum, and R23 limits the current through the diodes. C3 and C4 are included to keep the 709 stable. The output of the zero-crossing detector is connected to the input of the polarity detector (figure 16). For outputs from the zero-crossing detector greater than +0.6 V T6 is turned on and T7 is turned off, while for outputs more negative than -0.6 V T7 is turned on and T6 is turned off. For voltages between -0.6 V and +0.6 V both transistors are turned off, thus providing a zero indication. Polarity Indicator This consists of two high power NAND- gates (7440), connected as a set-reset flipflop (figure 17). During the measuring period this flipflop is either set or reset by the polarity detector de- pending on the polarity of the measured voltage and the appropriate LED is lit. The flipflop is necessary to store the polarity indication during the display period, when the output of the inte- grator (and hence of the zero-crossing detector) is zero. The Discharge Circuit There are in fact two discharge circuits, one of which is used depending on the polarity of the input signal. The circuit is shown in figure 18. When the input signal is positive, the output of the 74 1 in figure 14 is positive, and C2 charges so that the ‘right-hand’ end is more positive than the ‘left-hand’ end. This means that to discharge the capacitor the output of the integrator must be negative-going during the discharge 940 — elektor September 1975 dual slope dvm period. Current must therefore flow into point J. For a negative input signal the output of the integrator is negative, so the output must be positive-going during the discharge period. Current must therefore flow out of point J. The discharge circuits operate as fol- lows: when the input signal is positive point T is grounded by a control signal from the polarity indicator via the con- trol logic while point S remains high. T4 and T5 are therefore turned off, whilst T3 is turned on. +5.6 V therefore ap- pears across Zl. The voltage applied to R13, and therefore the current through R 1 3 into the integrator, can be adjusted by P2. When the measured voltage is negative, point T is ‘high’ and point S is ‘low’. T3 is turned off and T4 is turned on. -5.6 V appears across Z2 and the cur- rent through R 14 can be adjusted by P3. The Drift Compensator To prevent zero drift in the integrator and zero-crossing detector from causing Figure 19. The drift compensator. It is switched on via line U, and provides a feed- back from the output of the zero-crossing detector to the inverting input of the inte- Figure 20. The control logic. It receives signals from the reset pulse generator (E), the counter (G) and the polarity detector (0 and P). It drives the input chopper (H), the count gate (F), the discharge circuit (S and T), the polarity indicator (Q and R) and the drift compensator (U). Figure 21. The overall diagram. PI serves for zero adjustment of the integrator (see fig- ure 14). P2 and P3 serve to calibrate the DVM (see figure 18). inaccuracies feedback is applied round these circuits during the display period. During this time point U is low, so T13 is turned on and hence F3 is conducting (figure 19). Points M and K are connec- ted to the output of the zero-crossing detector and the inverting input of the integrator respectively, so any voltage offset on the output of the zero-crossing detector will be integrated, which will tend to null out the offset. During the measuring period point U is ‘high’, and the drift compensator is switched off so that the integrator and zero-crossing detector can function normally. Control logic The measurement sequence timing is performed by the control logic, the cir- cuit of which is given in figure 20. The , measurement sequence starts with a I positive pulse from the reset pulse gen- erator, which resets the counter via point D (figure 12). This pulse is also applied to point E of the control logic, and on the trailing edge of the pulse the JK flip flop (!4IC3) is set. The Q output connected to line H switches on the input chopper, whilst the Q output goes ‘low’ and sets the set-reset flipflop con- sisting of two NAND-gates. Output F thus goes “high’, opening the gate to the counter, so that it begins to count clock pulses. The drift compensator is also switched off via line U. A negative going pulse presets FF 1 in figure 1 2 via line C. ' The Q output of the 7473 holds the inputs of gates Ai and A 2 low via D8, which holds both inputs to the dis- charge circuit (S and T) high. The dis- charge circuit is therefore inoperative. When 100 clock pulses have been counted (time t 2 ) output G in figure 12 goes ‘low’, resetting the JK flipflop (V4IC3). The input chopper is now switched off via line H. In the meantime the flipflop comprising A 3 and A4 has been either set or reset by the polarity detector. Since the Q output of the 7473 is now ‘high’ the outputs of A 3 and A« can be gated through Ai and Aj to set the polarity indicator via lines 0 and R, and also to enable the appropriate part of the discharge cir- cuit. The counter continues to count clock pulses. Note that it is not necess- ary to reset the counter at time t 2 , as at the hundredth pulse it has reached zero! When the output of the integrator reaches zero the output of the zero- crossing detector is also zero. Both out- puts of the polarity detector go ‘high’, so the output of gate B 3 goes low, resetting the flipflop (B t and B 2 ), which disables the discharge circuit via D7 and Ai, A 2 . The counter gate is closed via line F so the count ceases. The display now indicates the measured value of the input voltage until the next reset pulse. H 942 — elektor September 1975 The principle of a LEP can be compared to a light-activated switch. The light source, however, has been replaced by the light pistol. By pulling the trigger of the LEP a short flash of light is emitted. This flash of light is produced by a lamp built into the barrel of the pistol. A microswitch operated by the trigger, connects a previously charged capacitor across the lamp. Via this low- resistance load the capacitor discharges quickly. As a result the lamp lights momentarily. To increase the intensity the lamp is briefly loaded with three to four times its nominal voltage. Moreover, the light flash is focussed by a biconvex lens into a parallel beam. Figure 1 shows the circuit diagram of the flash circuit. One possible practical realisation is shown in figure 2. The target has a light sensitive bull's eye. The circuits for hit and time indication are situated behind the target. Block diagram Figure 3 shows the block diagram of the hit and time indicator. A start-stop-oscillator (block 1 ) supplies the counting pulses for the timer. This timer (block 2) indicates the time be- tween start and hit with a resolution | of 1/100 second. If the bull’s eye is not hit within 9 seconds, the change-over from 8 to 9 is used by means of an AND-gate (block 3) to start a monostable multi- vibrator via block 4. The latter blocks the start-stop-oscillator for 2 seconds. After these 2 seconds the monostable resets. As a result the oscillator is started simultaneously with a second mono- stable (block 6). The second monostable resets the counter. By means of this second monostable the counter is maintained at zero for one more second, so that the total inter- ! val time is about 3 seconds. Figure 4 shows the diagrams of the pulse trains a, b and c. After this interval time the counter starts all over again. Figure 1. Circuit digram of the flash circuit. Figure 2. The practical construction can be very realistic, depending on the imagination of the builder. All components are easily accommodated inside the pistol. Figure 3. Block diagram of the LEP. Figure 4. Timing diagram of a: the output of MM1, b: the output of MM2 and c: the the oscillator output. Figure 5. Circuit of the ‘LEP complete with timer and traffic light'. slektor September 1975 — 943 This counting cycle can be interrupted only by a direct hit on the light sensitive resistor (block 7). Then a pulse is pro- duced which via the OR-gate (block 4) triggers the monostable multivibrator (block 5) so that the oscillator is stopped. Diagram Figure 5 gives the overall diagram of the hit and time indication. The indi- cation unit uses three cascaded 7490 decade counters with 7447 decoders driving Minitrons and needs little further discussion. The minitron has been chosen for the display. Any other seven-segment dis- play could, however, be used instead. The counter input is connected to an astable multivibrator. This multivibrator is formed by two nand gates (N5 and N6) with frequency-determining el- ements. A control unit starts and stops the oscillator, also resets the counter. An important part of the control unit is the hit detector built around T1 . Transistor T1 is adjusted so that it is normally conducting. The voltage div- ider consisting of R1 and R2 coupled by a capacitor can, however, briefly influence the bias of Tl. When a light flash hits R2, the base of Tl will be briefly grounded. As a result Tl blocks and by means of the trigger circuit consisting of N1 and N2, a short pulse going from ‘1’ to ‘0’ is generated. This pulse is fed to a NAND (N4) which triggers the monostable multivibrator MM1 connected behind. The sensitivity of the trigger circuit can to some extent be adjusted with PI. NAND N4 is used as an OR-gate here! As long as the output of the Schmitt 3 a trigger produces no pulse, it remains at the logic ‘P level. The same applies to the output of N3. This output remains ‘1’ until the last counter has reached position 1001. This happens after 9 seconds. As soon as the position 1 00 1 is reached, the output of N3 changes to ‘O’, so that MM 1 is triggered via N4. From then on it is impossible to trigger MM 1 from the hit indicator. The triggering of the monostable multi- vibrator MM1 causes the oscillator formed by the gates N5 and N6 to be blocked, because one input of N6 is connected to the Q-output of MM 1 . At the same time the set-reset flipflop (N7 plus N8) is reset by the 0 -signal on the input of N8. As a result the output of N8 becomes ‘P so that the red lamp, connected in the collector circuit of T2, 9*4 — elektor September 1975 lights up. The output of N7 goes to ‘O’, so that the green lamp in the collector circuit of T4 extinguishes. The circuit uses a kind of ‘traffic light’ as an indicator, which gives the start signal (green) and also indicates either that a hit has been made or that the playing time is over (red). The cycle time of MM1 is about 2 seconds. MM2 is started on the trailing edge of the output signal of Q of MM1 (that is after two seconds). The Q-output of MM2 then becomes ‘1’. This causes the amber lamp of the traffic lights to light up. The set-resei flipflop is reset on the trailing edge -. f the Q-signal. The red and amber lamp extinguish and the green one lights u,j. As soon as the Q-output signal of the first monostable MM1 becomes ‘1’ t.ie oscillator N5 plus N6 starts again. At the same time the counters are reset by the output signal of MM2, and kept ft ‘0’ during the cycle time of this monostable. Only when Q of MM2 becc mes ‘0’ again, can the counter start c mnting the pulses of the oscillator. This coincides with the traffic lights changing to green. For 9 seconds it is then permitted to shoot at the target. The cycle described above repeats itself. The functioning of the traffic light is slightly unconventional. Normally the amber lights gives warning that red is coming up. In this circuit, the amber warns that green is coming up (to indicate that the marksman may ‘go’ i.e. fire at the target). Construction The target is basically a board with a hole in the centre. This hole accommo- dates a lens with a focal length of about 20 mm. The light sensitive resistor of the hit detector is mounted at the principal focus behind the board. A lens with about the same focal length is mounted in the barrel of the pistol. A diaphragm with a lamp directly be- hind it is mounted at a distance of about V 20 mm from the lens in the pistol barrel I The batteries can be housed in the butt | of the pistol, which is a modified toy pistol of an ‘automatic’ type. The pistol should be fairly large, so that the components can easily be accom- modated inside it (see figure 2). The most realistic results are obtained if the pistol can retain the original cap- firing mechanism to produce a bang when the trigger is pulled. Conclusion Besides its original purpose (shooting) I this apparatus can also be used for test- 1 ing reaction speed. The possibility ofl cheating is then, however present be- 1 cause of the amber warning light and the I fixed time cycle. N. Beun The author does not pretend to present a revolutionary design, but only wishes to give a positive contribution to safety on the road, because in his opinion direction indication is something that leaves much to be desired with cyclists and moped riders. The design described here is a trafficator circuit which consists of an astable multi- vibrator and a switching darlington. Since the trafficator must also operate when the cycle is stationary, a battery is provided; if the dynamo is not to be used at all, Di can, of course, be omitted. The flashing frequency is 64 ‘flashes’ per minute and is reasonably constant owing to the characteristics of the multivibra- I tor. With the switching transistor (T 4 ) I used here, a maximum current of 0.4 A can be switched. Transistor T3 should l 1 have a low leakage current. The whole assembly (including batteries) should be shock and rattle-proof and mounted resiliently in a watertight cabi- net. Unauthorised use of the circuit is avoided by using a lock switch for S ia and Sib- 30 mhz amplifier elektor September 1975 — 945 w. Kummel n’S'i^sSKjlS^" S&gSs*- - Amplification of signals at frequencies up to 30 MHz without distortion and with a level frequency response requires fairly complex circuitry and may need expensive measuring equipment to set up. For driving digital equipment, however, distortion is less important, and in fact the amplifier described here clips the signal to provide a square wave output. The circuit will operate from a standard TTL (5 V) supply. Transistors used Experiments with various R.F. transis- tors proved unsuccessful due to the tendency of the circuit to ‘take-off into oscillation at umpteen megahertz, or not to work at all with the required supply voltage. Quite by chance a BC109Cwas soldered into the circuit, which at once performed perfectly. Further exper- iments showed that a large proportion of BC109C’s performed quite happily to above 30 MHz. Tests were carried out on 200 samples of BC107B, BC109C and unmarked ‘TUN’s’, and the results are shown in figure 1. The BC109C gave the best results, with 50% of the specimens tested being usable up to 30 MHz, and 1 0% still usable at 80 MHz. The Circuit The circuit of figure 2 is extremely simple. D1 and D2 limit the input voltage to protect the transistor. The transistor operates as a common-emitter amplifier. Figure 1 . Graph of percentage of usable devices versus operating frequency. Figure 2. The circuit of the amplifier. The output is fed to a pulse shaper con- sisting of 2 NAND Schmitt triggers (7413). This produces pulses with a rise time of less than 1 0 nanoseconds which will ensure reliable operation of the TTL circuits which the amplifier drives. Construction One or two points are worthy of note when building the circuit: 1 . Lead lengths should be kept short in view of the high frequencies involved, and in particular the output should be as close as possible to the input of the first 7413. 2. A transistor should be chosen with a D.C. current gain of greater than 200 as these are more likely to have a good high-frequency performance. 3. R2 provides D.C. biassing and feed - back and should be selected to give a collector voltage of about 1.25 V. 4. The supply filter (R4, C2, C3) is definitely necessary to avoid transients on the supply line driving the amplifier. If all these points are attended to, the amplifier should operate up to at least 30 MHz with an input sensitivity of 100 mV. Measurements on the local oscillators of receivers can be carried out using the amplifier, although a smaller input capacitor may be required to avoid detuning the oscillator. Alterna- tively, a direct connection may not be necessary if sufficient signal strength is available. In that case a capacitive coupling may be made by winding a short length of insulated wire around the end of a suitable resistor or capacitor in the circuit under test. Finally, it should be emphasised that this amplifier is not suitable for analogue amplification of signals, for instance, as an aerial preamplifier, since the signal is clipped. M 946 - elektor September 1975 e»\„ e Vi - &0mg? 6W' d ® ra o^ e ? The El 109 1C This COSMOS IC contains all the func- tions necessary for a 12 or 24 hour clock. It incorporates an oscillator cir- cuit requiring only an external 4. 1 94304 MHz crystal and trimmer ca- pacitor for operation. The display out- puts are multiplexed, and common cathode LED displays can be driven via single transistor buffer stages. A 1 second output is available to drive a flashing LED, and an output is also available that gives one pulse every 24 hours. Control inputs are provided in the form of reset (to 0.00), stop, slow and fast forward cycle, for setting the correct time. The circuit will operate on supplies up to +1 5 volts. The complete circuit The circuit of the complete clock is given in figure 1. Although the IC has good noise immunity a supply stabil- ization circuit is included that incor- porates interference suppression, for use in cars. The stabilizer is a simple zener reference driving an emitter follower. T13. However, due to the high current gain of the BC517 (typically 30,000) this circuit gives good regulation with few components. A filter consisting of Rl, R2 and Cl suppresses pulses from the car ignition system. Cl should be a low-inductance type of capacitor, preferably ceramic. The stabilizer pro- vides a supply to the clock of about 9 or 10 volts. The clock may also be powered from the mains by a simple power pack con- sisting of a transformer, bridge rectifier and smoothing capacitor. The trans- dock elektor September 1975 — 947 former should have a secondary voltage of about 8 V r.m.s. The output of the power pack can then be connected to the input of the stabilizer on the clock board. The display outputs of the IC operate on the well-known multiplex system (see ‘MOSCLOCK 5314, Elektor Dec. 1974). The multiplex frequency of 1024 Hz is derived, inside the IC, by dividing down the 4.194304 MHz refer- ence frequency. The displays are pulsed sequentially for approximately 61jis. This means that the segment resistors must be quite low to achieve reasonable brightness. Since the IC can sink only 0.1 mA at the digit outputs high gain transistors must be used for T8 - Til. For this reason the BC516 was chosen, which has a current gain of typically 30,000. The maximum collector current is also an adequate 400 mA. As the segment drive transistors T 1 - T7 carry only one- seventh the current (maximum) of T8 - T 1 1 , the BC 1 79C may be a suitable alternative. However, these should be selected for a minimum gain of 400. The crystal X and C6 are the external oscillator components. The trimmer ca- pacitor is used to adjust the timekeeping of the clock by ‘pulling’ the oscillator frequency. This may be done by con- necting a frequency counter in the period mode to the seconds output pin 13. Direct measurement at the os- cillator output should be avoided, as this may load the output and alter the frequency. Alternatively the time- keeping may be adjusted over a longer period using radio or telephone time signals. The seconds output drives T12 which causes the LED D2 to flash, thus show- ing that the clock is working. This is, of course, a refinement and may be omit- ted if the continual blinking of the LED is annoying. The clock may be connec- ted for a 1 2 or 24-hour cycle by means of pin 18. This is grounded for a Figure 1. The complete diagram of the car dock, including the stabilized supply. If necessary, the transistors T1. .. T7 can be re- placed by types such as the BC 179 C. Each of the latter must then be checked for current amplification factor. Figure 2. Lay-out and component arrange- ment of the main p.c.b. The wire bridge serving as the fixed adjustment for 12-hour or 24-hour dock requires extra attention (see text). Figure 3. The lay-out and component arrange- ment of the display p.c. board. This board is connected to the main p.c.board by means of the segment resistors (figure 2). I 948 — elektor September 1975 car cloc k I Figure 4. Showing how the main- and display L printed circuit boards are interconnected. 12-hour cycle and connected to positive supply for a 24-hour cycle. A link on the board makes this connection to the constructors requirements. Setting the clock Grounding the ‘reset’ input (pin 14) by means of SI will reset the display to 0.00. Grounding the ‘hold’ input (pin 15) will stop the clock. S3 causes the minute display to advance by one minute per second, while S3 causes the hours display to advance by one hour per second. C7 - CIO are included to minimise the effects of switch contact bounce. The use of double pole switches with their contacts wired in parallel will also help if needed. Construction To keep the finished clock as compact as possible a three-dimensional con- struction is employed with the display board mounted on top of the main p.c. board, and connected to it by the seg- ment resistors and wire links. The board and component layouts are given in figures 2 and 3, and the general appear- ance can be seen from figure 4 and the photograph. The link for 12/24-hour operation is at the bottom lefthand cor- ner of the main board. Only one link should be soldered in as otherwise the supply will be shorted out. The 1C should be the last component mounted on the main board and if it is soldered in then an earthed soldering iron must be used. For preference a socket should be used for the IC. Fi- nally, a 500 mA fuse should be connec- ted in series with the positive supply line when the unit is installed in the car. Variations on the design As mentioned earlier the clock may, if so desired, be run from a mains power pack. Like the MOSCLOCK a standby battery supply may also be incorporated if it is arranged that the supply to the displays is switched off in the event of a mains failure. (This reduces the power consumption to the few microamps needed to power the COSMOS cir- cuitry). Alternatively, the clock may be used as a travelling clock by powering it from a rechargeable NiCd battery, and incorporating a pushbutton to activate the display when required. For suitable circuits see MOSCLOCK 2, Elektor June 1975. H ■ elektor September 1975 - 949 mHRKBT Ke?niiiRKe?r!i»e? ■ COS/MOS opamp The CA3130 series of operational amplifiers, which RCA have intro- duced, offer a combination of the advantages of COS/MOS and bipolar transistors. A very high input impedance is achieved by the use of P-MOS (P-channel MOS) FETs in the input stage, while a latge output voltage swing is made possible by the use of a COS/MOS transistor pair for the output amplifier. The CA3130 is supplied in a TO-5 housing. Type CA3130T has normal leads, while those of type CA3130S are bent into a DIL configuration. Three variants of the electrical specification are available : CA3130T and CA3130S are the standard versions; CA3130AT and CA3130AS have improved input specifications; CA3130BT and CA3130BS are better still. Figure 1 shows the connections for the T versions. In the S ver- sions, connections 1, 2, 3 and 4 lie along one line while 5, 6, 7 and 8 lie along the other line. The CA3130 can work off asym- metrical power supplies from +5 to +16 V, or from ±2.5 to ±8 V symmetrical supplies. Figure 2 shows the block diagram of the CA3130. Input pins 2 and 3 can be driven down to 0.5 V below the negative supply (pin 4). In many applications the output can be swung very nearly positive or negative supply level For these reasons, the CA3130 is ideal for use with a single supply. Three class-A amplifier stages (shown as B, C and D in figure 2) provide the overall gain of the CA3130. A bias circuit (A) pro- vides two voltages for the first and the second stage. Pin 8 can be used for phase com- pensation, and/or to strobe the output stage into quiescence. When pin 8 is connected to the negative supply (pin 4), the out- put voltage at pin 6 rises almost to that of the positive supply volt- age on pin 7. This condition of essentially zero current drain in the output stage under the strobed ‘off condition can only be achieved when the ohmic load resistance presented to the ampli- fier is very high (e.g. when the amplifier is used to drive COS/ MOS digital circuits). Input stages The internal circuitry of the CA3130 is shown in figure 3. The circuit has a differential input stage with P-MOS field-effect transistors (T6 and T7), working into a mirror-pair of bipolar tran- sistors (T9 and T10) which function as load resistors. The output voltage of T10 is used to drive T1 1 in the second stage. Offset nulling, when desired, can be effected by connecting a 100 kS2 potentiometer across pins 1 and 5, with the slider con- nected to pin 4. Cascodc-connected P-MOS transis- tors T2 and T4 are the constant- current source for the input stage. The bias circuit for the current source will be described later. The diodes D5-D7 provide protec- tion for the gate against high- voltage transients due, for example, to static electricity. Second stage Most of the voltage gain in the CA3130 is provided by the second amplifier stage, consisting of bipolar transistor T1 1 and its case ode-connected load resistance provided by P-MOS transistors T3 and T5. The source of bias poten- tials for these P-MOS transistors will be described later. Miller- effect compensation (roll-off) is accomplished by simply con- necting a small capacitor between pins 1 and 8. A 47 pF capacitor provides sufficient compensation for stable unity-gain operation in most applications. Bias-Source Circuit At total supply voltages some- what above 8.3 V, resistor R2 and zener diode D9 serve to establish a constant voltage across the series-connected circuit, con- sisting of resistor Rl, diodes D1 to D4 inclusive, and P-MOS tran- sistor Tl. A tap at the junction of resistor Rl and diode D4 provides a gate-bias of about 4.5 V for P-MOS transistors T4 and T5 with respect to pin 7. A potential of about 2.2 V is developed across diode-connected transistor Tl with respect to pin 7 to provide gate bias for transistors T2 and T3. It should be noted that Tl is ‘mirror-connected’ to both T2 and T3. Since transistors Tl, T2 and T3 are designed to be ident- ical, the approximately 200 /i A in Tl establishes a similar current in T2 and T3 as constant-current sources for both the first and second amplifier stages, respect- ively. At supply voltages some- what less than 8.3 V, the zener diode becomes non-conductive and the potential, developed across series-connected Rl, D1 ... D4, and Tl, varies directly with variations in supply voltage. Consequently, the gate bias for T4, T5 and T2, T3 varies in accordance with supply voltage variations. This variation results in deterioration of the power supply rejection ratio (PSRR) at total supply voltages below 8.3 V. Operation at total supply voltages below about 4.5 V results in seriously degraded performance. 950 - elektor September 1975 market Output Stage The output stage consists of a drain-loaded inverting amplifier using COS/MOS transistors T8 and T1 2 operating in the class-A mode. When operating into very high resistance loads, the output can be swung within millivolts of either supply rail. Because the output stage is a drain-loaded amplifier, its gain is dependent upon the load impedance. Typical op-amp loads are readily driven by the output stage. Because large-signal excursions are non- linear, requiring feedback for good waveform reproduction, transient delays may be encountered. As a voltage follower, the amplifier can achieve 0.01 per cent accuracy levels, including the negative supply rail. Applications In figure 4 the CA3130 is used as a voltage follower. The bandwidth is 4 MHz and the slew rate is 10 VI Us. Figure 5 gives the circuit of a CA3l'30asa peak detector for positive voltages. It should be noted that, because of internal capacitances, the bandwidth for small signals is less than for large signals. For a 6 V peak-to-peak signal, the 3 dB bandwidth is 1.3 MHz, while for a 0.3 V peak- to-peak signal the 3 dB bandwidth is 240 kHz. In conclusion, figure 6 shows a circuit in which a CA3600E is used to boost the output power of the CA3130. The current con- sumption of a CA3600E as a class-A amplifier is 20 mA with a supply potential of 15 V. This arrangement increases the current- handling capacity of the CA3130 output stage by about x 2.5. With feedback, the closed-loop gain of the circuit is 48 dB. The 3 dB bandwidth is about 50 kHz. Output power is 150 mW with a total harmonic distortion of 10%. Figure 1. Connection diagram for the CA3130T. Figure 2. Block diagram of the CA3130 series of opamps. Figure 3. Basic circuit of the C A3 130 series of opamps. Figure 4. Voltage-follower circuit for a CA3130. Figure 5. Peak positive detector circuit for the CA3130. Figure 6. Increasing the output power of a CA3130 by con- necting a CA3600E. Table Typical values for the CA31 30 COS/MOS opamp. Supply voltage +5 V ... +16 V or ±2.5 V ... ±8 V Input offset voltage (V b = ±7.5 V) 8 mV Input offset current “« **&■* r^^tfs^SK ■'° iLsP* 't\P* ^® e 6 ® pP mO<° VS*" «£ $$*: >jjc- \* ^jo 0 ' ‘J, OP 8''®^%®%^ ' , o'*' > , 'V” S '* *f>3 3? $*£ «* f 5» SX* * 'K^f^ *V to* raj SINTEL elektor September 1975 — 14 Pin 0.1. L. Var. Voltage Reg. UK 300 Radio Control Transmitter UK 310 Radio Control Receiver UK 325 R/C 'GXC2' Channel Splitting Unit 1000 & 2000 Hz UK 330 GXC2 Channel Splitter Unit 1500 & 2500 Hz UK 330/A R/C Splitter Unit 1500 & 2500 Hz UK 345/A Superhet R/C Receiver UK 555 R/C 27 MHz Field Strength Meter UK 780 Electronic Metal Detector UK 875 Capacitive Discharge Electronic Ignition Unit. Neg. Earth Prices on Application 8 Pin D.I.L. Op.Amp semiconductor W 14 Pin D.I.L. I l^l , 2 Watt ■ / Audio D A Amp. semiconductor / / . 14 Pin D.I.L. | *''2-7 Stereo .<% / Pre-Amp Ay\A £1.65 AA motorola MC 14 Pin d > l. / * •% a » / Coiless / I jl OP Stereo Decoder £ 2 - 30 # FERRANTI radio chip £ 1.25 WM SIGNETICS /555V 7 ?S, 0 - IX - AAp 70p NATIONAL semiconductors Mullard Field Effect Transistors Mullard MOS Integrated Circuits Mullard Data Book 1974/75 Mullard Transistor Audio & Radio Circuits Basic Electronics Part 1 Basic Electronics Part 2 \ Basic Electronics Part 3 \ Basic Electronics Part 4 Basic Electronics Part 5 I Basic Electronics Part 6 / Basic Electronic Circuits Part 1 I Basic Electronic Circuits Part 2 l Basic Electronic Circuits Part 3 ) Basic Television Part 1 / Basic Television Part 2 Basic Television Part 3 \ Basic Electricity Part 1 1 Basic Electricity Part 2 Basic Electricity Part 3 Basic Electricity Part 4 / Basic Electricity Part 5 ELEKTOR Issues No. 1, 2, 3. 4 Full range of Elektor boards ex-stock number price MOS Clock (two boards . . . .£2.20 TV Sound £1.50 High quality Disc Preamp ... £ 0.99 Aerial Amplifier £ 0.99 A/D converter £ 0.92 P. and P. 15 pence. 283 Edgware Road, London W2. Tel. 01-262 8614 Hours of business 9.30 - 6.00 Monday to Saturday ELECTRONICS ☆ NEW* low-cost £ 1.45 1C insertion euch tool Trade Supplied all prices include VAT please add 20p to cover post ☆ NEW* low cost 55p 1C extraction euch tool Trade Supplied 954 — elektor September 1 975 £26.25 (CARRIAGE JOIN THE LARGE BAND OF CONSTRUCTORS. Don't miss your copy of HENRY'S NEW 1975 * OVER 5,000 ITEMS largest UK range of electronic components for home constructors. * 200 PAGES every aspect of electronics and components for amateurs and hobbyists - kits, projects, test gear. * DOZENS of new lines and new ranges. * MANY price reductions throughout the new Catalogue. * A Discount Voucher with every copy, worth L 50p. ALL PRICES INCLUSIVE OF VAT ssr. ELEKTOR VERLAG GMBH Internationale Funkausstellung 1975 Berlin 29.8. - 7.9.1975 Bitte besuchen Sie unseren Stand in Halle 7 Stand 731 Elektor Verlag GMBH, D-5133 Gangeltl, W-Germany, Tel I W- Germany) 02454 - 5055 Motorola Semiconductors Ltd.. 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